My Inquiry
My Account
Analog Devices Inc. ADP2120ACPZ-3.3-R7
- Part No.:
- ADP2120ACPZ-3.3-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-VFDFN Exposed Pad, CSP
- Datasheet:
-
ADP2120ACPZ-3.3-R7.pdf
- Description:
- IC REG BUCK 3.3V 1.25A 10LFCSP
- Quantity:
- Payment:
- Shipping:
Inventory:3,811
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADP2120ACPZ-3.3-R7 from Analog Devices is a fixed-output, 3.3 V, 1.25 A synchronous step-down DC-DC regulator in a 10-lead 3 mm × 3 mm LFCSP_WD package. It operates from 2.3 V to 5.5 V input, delivers ±1.5% output accuracy, features 1.2 MHz fixed switching frequency with synchronization capability (1–2 MHz), and supports PWM/PPM mode selection via SYNC/MODE pin for high efficiency across load range.
For engineers reviewing the ADP2120ACPZ-3.3-R7 datasheet, ADP2120ACPZ-3.3-R7 pinout, ADP2120ACPZ-3.3-R7 application, or ADP2120ACPZ-3.3-R7 equivalent, this page provides verified technical context, validated pin functions, confirmed operating parameters, real-world application mappings, and two rigorously cross-checked alternative parts for point-of-load power design.
Technical Context
The ADP2120ACPZ-3.3-R7 uses a current-mode, constant-frequency PWM control architecture with integrated P-channel high-side (145 mΩ typ) and N-channel low-side (70 mΩ typ) MOSFETs. Its peak current limit is 1.6–2.4 A (typ–max), and it includes slope compensation to prevent subharmonic oscillation above 50% duty cycle.
It implements precision enable threshold (1.2 V typ, 100 mV hysteresis), integrated soft start (853 µs at 1.2 MHz), voltage tracking (TRK pin), and power-good flag (PGOOD open-drain with 110% rising threshold). Protection includes UVLO (2.3 V rising), OVP, OCP, and thermal shutdown (150°C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 3.3 V ±1.5% - eliminates external feedback resistors and ensures stable rail for FPGA I/O or microcontroller peripherals. |
| Max Output Current | 1.25 A continuous - supports moderate-power digital loads such as ARM Cortex-M7 SoCs or multi-channel ADCs. |
| Input Voltage Range | 2.3 V to 5.5 V - compatible with single-cell Li-ion, USB 5 V, or regulated 3.3 V/5 V intermediate rails. |
| Switching Frequency | 1.2 MHz fixed (1.02–1.38 MHz typ) - enables use of compact 1.5 µH inductors and reduces EMI filtering burden. |
| Quiescent Current | 680–900 µA (switching, no load) - balances light-load efficiency and fast transient response in always-on subsystems. |
| Package | 10-lead LFCSP_WD (3 mm × 3 mm, exposed pad) - provides low thermal resistance (θJA = 40°C/W) and robust PCB thermal dissipation. |
| Protection Features | UVLO, OVP, OCP, thermal shutdown, and PGOOD - enables autonomous fault handling without external supervision circuitry. |
Pinout & Package
ADP2120ACPZ-3.3-R7 is housed in a 10-lead, 3 mm × 3 mm LFCSP_WD package with an exposed thermal pad soldered to PCB ground for optimal heat transfer.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 VIN | Bias supply input | Provides internal circuit bias; requires 0.1 µF bypass capacitor and 10 Ω series resistor to PVIN for noise isolation. |
| 2 PVIN | Main power input | High-current input path; connects directly to source and requires local 22 µF X5R ceramic capacitor to PGND. |
| 3 SW | Switch node | Drives external inductor; carries high di/dt; must be routed with minimal loop area to reduce EMI. |
| 4 PGND | Power ground | High-current return for MOSFETs; must connect directly to power plane under exposed pad and inductor. |
| 5 GND | Analog ground | Reference for FB, EN, TRK; should tie to clean analog ground plane, separate from noisy PGND where possible. |
| 6 FB | Feedback sense | Internally connected to 3.3 V output; not used in fixed-version - shorted internally to output pin per datasheet. |
| 7 TRK | Voltage tracking input | Enables output voltage to follow master rail (e.g., FPGA core); connect to resistor divider or tie to VIN if unused. |
| 8 PGOOD | Power-good flag | Open-drain output asserting when FB ≥110%; requires external pull-up to ≤5.5 V for system sequencing. |
| 9 SYNC/MODE | Sync clock or PFM/PWM select | Drive with 1–2 MHz clock for synchronization; tie to GND for PFM mode or VIN for forced PWM operation. |
| 10 EN | Enable control | Precision 1.2 V threshold with 100 mV hysteresis; internal 1 MΩ pull-down prevents floating; connect to VIN for auto-start. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated high- and low-side MOSFETs | 145 mΩ P-FET + 70 mΩ N-FET - eliminates external power switches and reduces BOM count while enabling >90% efficiency at 1 A. |
| Selectable PWM/PPM operation | SYNC/MODE pin configures CCM-only (PWM) or automatic light-load PFM - extends battery life in portable systems without sacrificing transient performance. |
| Voltage tracking (TRK) | Tracks master rail with ±15 mV offset - supports safe power sequencing for FPGAs requiring I/O voltage to ramp after core voltage. |
| Integrated soft start | Fixed 853 µs (at 1.2 MHz) - limits inrush current during startup and prevents input rail droop in multi-rail systems. |
| Power-good flag with deglitch | 16-clock-cycle deglitch (≈13.3 µs at 1.2 MHz) - rejects noise-induced false trips and enables reliable system reset assertion. |
| Startup with precharged output | Prevents reverse inductor current - avoids discharging pre-biased outputs (e.g., hot-swap or backup rails), ensuring safe turn-on. |
Applications
| Point-of-Load Conversion | Communications Equipment |
|---|---|
Use Scenario: Local 3.3 V rail generation for Ethernet PHYs or SFP+ modules on a dense switch PCB. IC Role / Device Role / Timing Role: Primary buck converter delivering regulated 3.3 V at up to 1.25 A with tight load regulation (0.08%/A). Use Value: Compact 3 mm × 3 mm footprint saves board space; PFM mode maintains >85% efficiency at 10 mA idle current. |
Use Scenario: Powering baseband processor I/O banks in small-cell LTE radio units. IC Role / Device Role / Timing Role: Fixed-output DC-DC regulator synchronized to system clock via SYNC/MODE pin to minimize beat-frequency EMI. Use Value: 1.2 MHz switching allows use of low-profile 1.5 µH inductors; PGOOD enables precise power sequencing with FPGA configuration logic. |
| Industrial Instrumentation | Medical Monitoring Devices |
Use Scenario: Supplying isolated ADC front-end and microcontroller in handheld multimeter with Li-ion battery input. IC Role / Device Role / Timing Role: Efficient step-down regulator operating from 3.0–4.2 V battery range, supporting dynamic load steps from sleep to active measurement. Use Value: UVLO (2.3 V) and thermal shutdown ensure safe operation during battery depletion or enclosure overheating. |
Use Scenario: Generating patient-connected 3.3 V logic rail in portable ECG monitor with strict leakage and reliability requirements. IC Role / Device Role / Timing Role: Low-noise, protected DC-DC stage with tracking capability to coordinate with isolated 1.8 V analog front-end. Use Value: Internal compensation and fixed 3.3 V output eliminate external components, reducing risk of field failure and easing regulatory certification. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62130ARGTR | 3.0 V fixed output (not 3.3 V); 3 A rating; 2.5–6 V input; 2.5 MHz switching; no TRK pin. | Higher current and frequency, but lacks voltage tracking and fixed 3.3 V option - requires redesign for I/O rail coordination. | Select when higher output current or faster transient response is required, and tracking is unnecessary. |
| RT7295BGJ5 | 3.3 V fixed output; 2 A rating; 4.5–18 V input; 500 kHz switching; integrated compensation; no PFM mode. | Wider input range suits 12 V intermediate rails, but lower switching frequency demands larger magnetics; no light-load efficiency optimization. | Select for industrial 12 V input systems where size is less critical than cost, and continuous conduction suffices. |
Compared with TPS62130ARGTR and RT7295BGJ5, ADP2120ACPZ-3.3-R7 uniquely combines exact 3.3 V fixed output, voltage tracking, 1.2 MHz operation in compact LFCSP, and seamless PFM/PWM transition - making it optimal for space-constrained, multi-rail embedded systems requiring precise sequencing and battery-aware efficiency.
Availability
ADP2120ACPZ-3.3-R7 is available at Aetrix Electronics and suitable for point-of-load conversion, communications equipment, industrial instrumentation, medical monitoring devices, and consumer electronics requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for ADP2120ACPZ-3.3-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision, industrial, automotive, and communications markets since 1965.
The ADP2120ACPZ-3.3-R7 belongs to Analog Devices' ADP21xx family of compact, high-efficiency synchronous buck regulators designed specifically for low-voltage, medium-current point-of-load applications in space- and power-sensitive embedded systems.
FAQ
What is the maximum output current capability of the ADP2120ACPZ-3.3-R7?
The ADP2120ACPZ-3.3-R7 delivers up to 1.25 A continuous output current under typical thermal conditions (θJA = 40°C/W, 25°C ambient). Its peak current limit is specified from 1.6 A (min) to 2.4 A (max) at 3.3 V input, providing margin for transient loads. Derating is required above 85°C ambient or with limited airflow.
Does the ADP2120ACPZ-3.3-R7 require external feedback resistors?
No. The ADP2120ACPZ-3.3-R7 is a fixed-output variant with internal feedback set to 3.3 V. Pin 6 (FB) is internally connected to the output; no external resistors are needed. This simplifies layout, improves accuracy, and eliminates resistor tolerance drift effects on regulation.
How does the SYNC/MODE pin function on the ADP2120ACPZ-3.3-R7?
The SYNC/MODE pin serves dual purpose: when driven by an external 1–2 MHz clock, it synchronizes switching frequency; when tied to GND, it enables PFM mode for light-load efficiency; when tied to VIN, it forces continuous PWM operation. No external components are required for either function.
Can the ADP2120ACPZ-3.3-R7 safely start up with a precharged output capacitor?
Yes. The ADP2120ACPZ-3.3-R7 includes dedicated circuitry that detects precharged output voltage and holds both MOSFETs off until the soft-start voltage exceeds the FB voltage. This prevents reverse inductor current and avoids discharging the output capacitor during turn-on - critical for hot-swap and redundant power systems.
What thermal considerations apply to the ADP2120ACPZ-3.3-R7 package?
The ADP2120ACPZ-3.3-R7 uses a 10-lead LFCSP_WD package with an exposed thermal pad that must be soldered to a PCB ground plane using ≥4 thermal vias. With proper layout, its junction-to-ambient thermal resistance is 40°C/W, enabling 1.25 A operation at up to 85°C ambient. Thermal shutdown activates at 150°C with 25°C hysteresis.
ADP2120ACPZ-3.3-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.3V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 3.3V
- Voltage - Output (Max):
- -
- Current - Output:
- 1.25A
- Frequency - Switching:
- 1.2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-LFCSP-WD (3x3)
ADP2120ACPZ-3.3-R7 FAQ
1.How can I place an order for ADP2120ACPZ-3.3-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2120ACPZ-3.3-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2120ACPZ-3.3-R7 reliable?
The price and inventory of ADP2120ACPZ-3.3-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2120ACPZ-3.3-R7 is usually 5 days.
3.What payment methods are accepted for ADP2120ACPZ-3.3-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2120ACPZ-3.3-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2120ACPZ-3.3-R7?
ADP2120ACPZ-3.3-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2120ACPZ-3.3-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2120ACPZ-3.3-R7?
For technical support, including ADP2120ACPZ-3.3-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2120ACPZ-3.3-R7 requirements.
6.How does Aetrix verify that ADP2120ACPZ-3.3-R7 is sourced from the original manufacturer or authorized distributors?
All ADP2120ACPZ-3.3-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2120ACPZ-3.3-R7 meets industry standards.
7.What is the process for return or replacement of ADP2120ACPZ-3.3-R7?
All ADP2120ACPZ-3.3-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2120ACPZ-3.3-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2120ACPZ-3.3-R7 part is unused and in its original packaging.
Return procedure for ADP2120ACPZ-3.3-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADP2120ACPZ-3.3-R7 Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
