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Analog Devices Inc. ADP2140ACPZ1228R7
- Part No.:
- ADP2140ACPZ1228R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad, CSP
- Datasheet:
-
ADP2140ACPZ1228R7.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 10LFCSP
- Quantity:
- Payment:
- Shipping:
Inventory:1,727
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Product details
Overview
ADP2140ACPZ1228R7 from Analog Devices is a dual-output power management IC integrating a 600 mA synchronous buck regulator and a 300 mA low-noise LDO in a single 10-lead 3 mm × 3 mm LFCSP package. It operates from 2.3 V to 5.5 V input, delivers buck output from 1.0 V to 3.3 V and LDO output from 0.8 V to 3.3 V, and achieves 3 MHz switching frequency with 20 μA quiescent current in PSM mode - optimized for battery-powered portable electronics requiring high efficiency and ultra-low standby power.
For engineers reviewing the ADP2140ACPZ1228R7 datasheet, ADP2140ACPZ1228R7 pinout, ADP2140ACPZ1228R7 application, or ADP2140ACPZ1228R7 equivalent, key selection criteria include its dual-rail sequencing capability, 110 mV LDO dropout at 300 mA, 65 dB PSRR at 10 kHz, 40 μVrms LDO noise at 1.2 V, and integrated power-good indicator supporting reliable system startup in space-constrained mobile platforms.
Technical Context
The ADP2140ACPZ1228R7 employs a proprietary high-speed current-mode PWM control scheme for the buck section, enabling fast transient response and stable operation across load and line variations. Its variable-frequency power-save mode (PSM) reduces switching frequency under light loads to minimize quiescent current - critical for extending battery life in always-on subsystems.
The LDO operates in split-supply mode with VIN2 as low as 1.65 V, allowing direct connection to the buck output to improve overall system efficiency. It features internal compensation, soft-start, undervoltage lockout (UVLO), thermal shutdown (150°C), and short-circuit protection - all implemented without external components beyond four passive devices.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 600 mA - supports core logic rails (e.g., ARM Cortex-A/M cores) without external boost or parallel stages. |
| LDO Output Current | 300 mA - sufficient for noise-sensitive analog/RF circuitry (e.g., ADCs, PLLs, audio codecs) with minimal board area. |
| Switching Frequency | 2.55–3.15 MHz - enables use of sub-1 μH inductors and small ceramic capacitors, reducing solution size to ~90 mm². |
| LDO Dropout Voltage | 110 mV @ 300 mA - allows regulation from buck output (e.g., 1.8 V buck → 1.69 V LDO) with <2% voltage loss. |
| LDO Output Noise | 40 μVrms @ 1.2 V - meets stringent noise requirements for precision analog signal chains and RF front-ends. |
| Quiescent Current | 20 μA (buck, PSM mode) / 22 μA (LDO, zero load) - extends shelf life and runtime in deep-sleep states of IoT sensors and wearables. |
| Power-Good Threshold | 92% rising / 86% falling - provides robust reset signaling for microcontrollers and FPGAs during brown-out recovery. |
Pinout & Package
ADP2140ACPZ1228R7 is housed in a 10-lead, 0.75 mm pitch, 3 mm × 3 mm LFCSP package with exposed thermal pad electrically connected to PGND. The exposed pad must be soldered to a PCB ground plane for optimal thermal performance (θJA = 35.3°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - PGND | Power Ground | Main return path for buck switch current; must be low-inductance connection to PCB ground plane. |
| 2 - SW | Buck Switch Node | Connects internal PFET/NFET to external inductor; requires tight layout to minimize EMI and ringing. |
| 3 - AGND | Analog Ground | Reference for FB and LDO feedback; isolated from PGND except at single-point ground to reduce noise coupling. |
| 4 - FB | Buck Feedback Input | Senses regulated buck output via resistor divider; sets output voltage with ±1% initial accuracy. |
| 5 - VIN2 | LDO Input Supply | Accepts 1.65–5.5 V; can be tied to buck output or separate rail for flexible power-tree design. |
| 6 - VOUT2 | LDO Output | Delivers clean, low-noise output; requires ≥1 μF ceramic capacitor with ESR ≤1 Ω for stability. |
| 7 - EN2 | LDO Enable Control | Logic-high enables LDO; left unconnected for autosequencing where EN1 controls both regulators. |
| 8 - EN1 | Buck Enable / Sequencing Trigger | Active-high enable; in autosequencing mode, rising edge initiates buck first, then LDO after 5 ms delay. |
| 9 - PG | Open-Drain Power-Good | Asserts high when both outputs are within 92%–106% of nominal; pulls low during fault or undervoltage. |
| 10 - VIN1 | Buck Input Supply | Accepts 2.3–5.5 V; powers buck stage and internal bias circuits; requires ≥10 μF input capacitance. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enable inputs (EN1/EN2) | Supports user-defined power-up sequencing (e.g., buck-first, LDO-first, or simultaneous) without external logic. |
| Integrated power-good (PG) indicator | Monitors both buck and LDO outputs simultaneously; eliminates need for external supervisors or comparators. |
| Split-supply LDO architecture | Allows VIN2 as low as 1.65 V - enables post-regulation of buck output to reduce noise while maximizing efficiency. |
| Internal compensation & soft-start | Reduces BOM count by eliminating external compensation network; soft-start limits inrush current during startup. |
| Thermal and current-limit protection | Auto-recovery thermal shutdown (150°C) and cycle-by-cycle current limit prevent damage during overload or PCB overheating. |
Applications
| Mobile Phone Power Management | Digital Camera Sensor Biasing |
|---|---|
|
Use Scenario: Dual-rail supply for application processor (1.2 V core) and image signal processor (1.8 V I/O) in slim smartphone designs. IC Role / Device Role: Primary PMIC delivering tightly regulated, sequenced voltages with minimal footprint and thermal overhead. Use Value: Enables 3 mm × 3 mm solution size and 20 μA quiescent current - directly extending talk time and reducing thermal throttling. |
Use Scenario: Clean bias for CMOS image sensor analog front-end and ADC reference in compact digital cameras. IC Role / Device Role: Low-noise LDO (40 μVrms) post-regulating buck output to suppress switching ripple on sensitive analog rails. Use Value: Achieves >65 dB PSRR at 10 kHz - prevents switching noise from degrading SNR in 12-bit+ imaging pipelines. |
| Portable Audio Codec Supply | Wearable Health Sensor Hub |
|
Use Scenario: Dedicated low-noise supply for stereo audio DAC and headphone amplifier in Bluetooth headphones. IC Role / Device Role: LDO output (VOUT2) set to 1.8 V with 110 mV dropout - maintains regulation from declining Li-ion cell voltage (3.6 V → 2.8 V). Use Value: 40 μVrms noise ensures THD+N < −95 dB - meeting premium audio fidelity requirements without additional filtering. |
Use Scenario: Ultra-low-power dual-rail supply for optical heart-rate sensor, MCU, and BLE radio in fitness trackers. IC Role / Device Role: Buck powers MCU core (1.0 V @ 200 mA); LDO powers analog sensor interface (3.0 V @ 50 mA) with 22 μA zero-load IQ. Use Value: Enables 7-day battery life in continuous monitoring mode - validated by 20 μA PSM quiescent current and <0.3 μA shutdown current. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DC-DC + LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62740DRYR | Single 300 mA buck only; no integrated LDO; 3.6 μA IQ in DCS-Control™ mode. | Lacks LDO rail - requires external low-noise regulator for analog sections, increasing BOM and layout complexity. | Choose when only one regulated rail is needed and lowest possible IQ dominates design priority. |
| MAX8640YETA+ | 2.25 MHz buck + 300 mA LDO; 25 μA buck IQ; no PG pin; 16-pin TQFN package (4 mm × 4 mm). | Larger footprint (16 mm² vs. 9 mm²); lacks power-good output - necessitates external reset IC for system reliability. | Choose if existing layout accommodates larger package and PG functionality is not required. |
Compared with TPS62740DRYR and MAX8640YETA+, ADP2140ACPZ1228R7 uniquely combines 3 MHz switching, integrated PG, 9 mm² footprint, and dual enable sequencing - making it optimal for space- and noise-constrained portable systems needing guaranteed power-rail coordination.
Availability
ADP2140ACPZ1228R7 is available at Aetrix Electronics and suitable for mobile phones, digital cameras, portable audio devices, wearable health monitors, and battery-powered industrial sensors requiring stable component supply with full traceability and long-term lifecycle support.
Supply support for ADP2140ACPZ1228R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The ADP2140ACPZ1228R7 belongs to Analog Devices' Power Management portfolio, engineered specifically for ultra-compact, high-efficiency power delivery in portable and battery-operated consumer electronics.
FAQ
What is the recommended input capacitor for ADP2140ACPZ1228R7?
The ADP2140ACPZ1228R7 requires a minimum 10 μF X7R/X5R ceramic input capacitor (CIN) placed close to VIN1 and PGND pins. This value ensures stable operation across temperature and voltage ranges, suppresses input ripple, and supports peak current demands during load transients. Lower ESR (<0.01 Ω) improves high-frequency noise rejection. Y5V/Z5U types are explicitly discouraged due to capacitance drift.
Does ADP2140ACPZ1228R7 support independent enable control of buck and LDO?
Yes, ADP2140ACPZ1228R7 supports independent control: EN1 enables the buck regulator, and EN2 enables the LDO. When EN2 is left floating, the device enters autosequencing mode where EN1 rising edge triggers buck startup first, followed by LDO after a fixed 5 ms delay - ensuring proper power-rail ordering without external timing components.
What is the maximum allowable junction temperature for ADP2140ACPZ1228R7?
The ADP2140ACPZ1228R7 has a maximum operating junction temperature of +125°C, with thermal shutdown activating at +150°C (with 20°C hysteresis). To maintain reliability, design must ensure TJ stays within specification using the formula TJ = TA + (PD × θJA), where θJA = 35.3°C/W for the 3 mm × 3 mm LFCSP package on a standard 4-layer board.
Can ADP2140ACPZ1228R7's LDO be powered from its own buck output?
Yes - the LDO input (VIN2) accepts voltages as low as 1.65 V, making it fully compatible with being powered directly from the buck output (e.g., 1.8 V buck → 1.8 V LDO). This configuration improves overall system efficiency by eliminating intermediate voltage drops and reduces external component count, while leveraging the LDO's 65 dB PSRR to filter buck switching noise.
How does the power-good (PG) pin function on ADP2140ACPZ1228R7?
The PG pin on ADP2140ACPZ1228R7 is an open-drain output that goes high only when both the buck output (sensed at FB) and LDO output (VOUT2) exceed 92% of their nominal values. It remains high until either output falls below 86% of nominal. This dual-rail monitoring ensures microcontrollers or FPGAs receive a valid reset signal only when all critical supplies are stable and within tolerance.
ADP2140ACPZ1228R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.2V, 600mA
- Voltage/Current - Output 2:
- 2.8V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-LFCSP-WD (3x3)
ADP2140ACPZ1228R7 FAQ
1.How can I place an order for ADP2140ACPZ1228R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2140ACPZ1228R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2140ACPZ1228R7 reliable?
The price and inventory of ADP2140ACPZ1228R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2140ACPZ1228R7 is usually 5 days.
3.What payment methods are accepted for ADP2140ACPZ1228R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2140ACPZ1228R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2140ACPZ1228R7?
ADP2140ACPZ1228R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2140ACPZ1228R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2140ACPZ1228R7?
For technical support, including ADP2140ACPZ1228R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2140ACPZ1228R7 requirements.
6.How does Aetrix verify that ADP2140ACPZ1228R7 is sourced from the original manufacturer or authorized distributors?
All ADP2140ACPZ1228R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2140ACPZ1228R7 meets industry standards.
7.What is the process for return or replacement of ADP2140ACPZ1228R7?
All ADP2140ACPZ1228R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2140ACPZ1228R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2140ACPZ1228R7 part is unused and in its original packaging.
Return procedure for ADP2140ACPZ1228R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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