Analog Devices Inc. ADP2140ACPZ1812R7
- Part No.:
- ADP2140ACPZ1812R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 10-VFDFN Exposed Pad, CSP
- Datasheet:
-
ADP2140ACPZ1812R7.pdf
- Description:
- IC REG DL BUCK/LNR SYNC 10LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:2,113
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADP2140ACPZ1812R7 from Analog Devices is a dual-output power management IC integrating a 600 mA synchronous buck regulator and a 300 mA low-noise LDO in a single 10-lead 3 mm × 3 mm LFCSP package. It operates from 2.3 V to 5.5 V input, delivers 1.8 V buck output and 1.2 V LDO output, and achieves 3 MHz switching frequency with 20 μA quiescent current in PSM mode - optimized for battery-powered portable electronics requiring tight voltage regulation and minimal standby power.
For engineers reviewing the ADP2140ACPZ1812R7 datasheet, ADP2140ACPZ1812R7 pinout, ADP2140ACPZ1812R7 application, or ADP2140ACPZ1812R7 equivalent, key selection criteria include its dual-rail sequencing capability, 110 mV LDO dropout at 300 mA, 65 dB PSRR at 10 kHz, 40 μVrms LDO noise at 1.2 V, and integrated power-good indicator for system-level power integrity validation.
Technical Context
The ADP2140ACPZ1812R7 implements a high-speed current-mode PWM control architecture for the buck section, enabling fast transient response and stable operation with minimal external components. Its variable-frequency power-save mode (PSM) reduces switching frequency under light loads to maintain high efficiency across wide load ranges.
The LDO operates in split-supply configuration - accepting VIN2 as low as 1.65 V - and is designed to be powered either directly from the buck output or an independent rail. This enables post-regulation of buck noise and supports flexible power sequencing via dual EN pins (EN1/EN2), including autosequencing where the higher-voltage output enables first.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Voltage | 1.8 V ±1% - factory-trimmed fixed output eliminates need for external feedback resistors. |
| LDO Output Voltage | 1.2 V ±1% - precision fixed output suitable for core logic or analog circuitry requiring ultra-low noise. |
| Switching Frequency | 3.0 MHz nominal - enables use of small 1 µH inductors and compact 0603/0402 passives for <90 mm² total solution size. |
| Buck Quiescent Current | 20 μA in PSM mode - extends battery life in always-on or low-duty-cycle portable applications. |
| LDO Dropout Voltage | 110 mV @ 300 mA - allows efficient regulation from low-input rails such as 1.32 V buck output or single-cell Li+. |
| LDO Output Noise | 40 μVrms (10 Hz–100 kHz) at 1.2 V - meets stringent noise requirements for RF, audio, and precision ADC/DAC supplies. |
| Power-Good Threshold | 92% rising / 86% falling - provides robust system reset signaling with 6% hysteresis to prevent chatter during marginal conditions. |
Pinout & Package
ADP2140ACPZ1812R7 is housed in a 10-lead, 0.75 mm height, 3 mm × 3 mm LFCSP package with exposed thermal pad electrically connected to PGND. The pad must be soldered to a PCB ground plane for optimal thermal performance and EMI suppression.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (PGND) | Power Ground | Main return path for buck switch current; connects to PCB ground plane and exposed pad. |
| 2 (SW) | Switch Node | Connection between internal PFET/NFET and external inductor; requires low-inductance layout for EMI control. |
| 3 (AGND) | Analog Ground | Reference for FB and LDO feedback; must be star-connected to PGND near device to avoid noise coupling. |
| 4 (FB) | Buck Feedback Input | Monitors regulated buck output; not used in fixed-output variants like ADP2140ACPZ1812R7. |
| 5 (VIN2) | LDO Input Supply | Accepts 1.65 V–5.5 V; can be tied to buck output (e.g., 1.8 V) to minimize dropout and improve efficiency. |
| 6 (VOUT2) | LDO Output | Delivers regulated 1.2 V; requires ≥1 µF ceramic output capacitor with ≤1 Ω ESR for stability. |
| 7 (EN2) | LDO Enable Control | Logic-high enables LDO; left unconnected for autosequencing mode where EN1 controls both outputs. |
| 8 (EN1) | Buck Enable / Sequencing Trigger | Active-high enable for buck; in autosequencing, rising edge initiates buck first, then LDO after 5 ms delay. |
| 9 (PG) | Open-Drain Power-Good | Asserts high when both VOUT and VOUT2 reach ≥92% of nominal; requires external pull-up resistor. |
| 10 (VIN1) | Buck Input Supply | Accepts 2.3 V–5.5 V; powers buck section and internal bias circuits; decoupled with ≥10 µF ceramic capacitor. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Buck + LDO | Single-chip dual-rail solution reduces BOM count, board area, and design complexity versus discrete regulators. |
| Ultra-Low LDO Quiescent Current | 22 μA at zero load - preserves battery capacity in standby without compromising LDO regulation accuracy. |
| High PSRR LDO | 65 dB @ 10 kHz - effectively filters ripple and noise from buck output when used as post-regulator. |
| Programmable Power Sequencing | Two independent enable inputs support manual sequencing, autosequencing, or independent control of buck/LDO rails. |
| Robust Protection Suite | Includes undervoltage lockout (2.3 V rise), thermal shutdown (150 °C), short-circuit current limit, and soft-start (150 μs). |
Applications
| Mobile Phone Baseband | Digital Camera Image Sensor |
|---|---|
Use Scenario: Powering application processor I/O and memory interface in smartphone mainboard with tight space constraints. IC Role / Device Role / Timing Role: Provides tightly regulated 1.8 V I/O supply (buck) and ultra-clean 1.2 V core voltage (LDO) with synchronized startup. Use Value: Eliminates need for separate LDO IC, reduces PCB area by >30%, and ensures clean core voltage for error-free DDR interface timing. |
Use Scenario: Supplying CMOS image sensor and ISP in compact digital camera modules. IC Role / Device Role / Timing Role: Delivers low-noise 1.2 V analog supply (LDO) and 1.8 V digital rail (buck) with precise power-good assertion for sensor initialization. Use Value: 40 μVrms LDO noise prevents fixed-pattern noise in captured images; PG signal ensures reliable sensor firmware boot sequence. |
| Portable Audio DAC/ADC | Wearable Health Monitor SoC |
Use Scenario: Biasing high-resolution audio codec in Bluetooth headphones or portable DAC dongles. IC Role / Device Role / Timing Role: Supplies 1.2 V ultra-low-noise analog reference (LDO) and 1.8 V digital domain (buck), with PSRR filtering switching noise. Use Value: 65 dB PSRR at 10 kHz suppresses buck ripple from entering audio band, enabling >110 dB SNR performance. |
Use Scenario: Powering ultra-low-power MCU, biosensor front-end, and BLE radio in wrist-worn health devices. IC Role / Device Role / Timing Role: Delivers 1.8 V buck output for MCU I/O and 1.2 V LDO output for analog sensor interface, with 20 μA PSM quiescent current. Use Value: Extends coin-cell battery life beyond 6 months in sleep mode while maintaining fast wake-up response via integrated soft-start. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62745DSSR | Single 300 mA buck + LDO; no dual enable sequencing; 1.8 V buck only; LDO adjustable (0.9–3.3 V); 2.5 MHz switching. | Lacks autosequencing and fixed 1.2 V LDO; requires external resistor for LDO setpoint; smaller solution size but less flexibility. | Choose when fixed 1.2 V LDO is unnecessary and board space is more critical than sequencing control. |
| MAX8646ETA+ | 3 MHz buck + 300 mA LDO; 1.8 V buck / 1.2 V LDO; but no PG pin, no autosequencing, higher LDO quiescent current (45 μA). | No power-good monitoring or programmable sequencing; less suitable for systems requiring coordinated rail bring-up or reset signaling. | Choose if PG and sequencing are not required and cost is prioritized over system-level reliability features. |
Compared with TPS62745DSSR and MAX8646ETA+, the ADP2140ACPZ1812R7 uniquely combines fixed dual outputs, dual-enable sequencing, open-drain PG, and industry-leading 22 μA LDO quiescent current - making it optimal for space-constrained, battery-sensitive systems demanding predictable power-up behavior and ultra-low noise.
Availability
ADP2140ACPZ1812R7 is available at Aetrix Electronics and suitable for mobile phones, digital cameras, portable audio devices, and wearable health monitors requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for ADP2140ACPZ1812R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The ADP2140ACPZ1812R7 belongs to Analog Devices' Power Management IC portfolio, engineered specifically for portable and battery-powered applications where ultra-low quiescent current, small solution size, and dual-rail integration are critical design requirements.
FAQ
What is the output voltage configuration of the ADP2140ACPZ1812R7?
The ADP2140ACPZ1812R7 is a factory-configured variant delivering a fixed 1.8 V buck output and a fixed 1.2 V LDO output. These voltages are trimmed during production and do not require external feedback resistors - simplifying layout and ensuring ±1% accuracy across temperature and load.
Does the ADP2140ACPZ1812R7 support independent enable control of the buck and LDO sections?
Yes, the ADP2140ACPZ1812R7 supports independent control via EN1 (buck enable) and EN2 (LDO enable). When EN2 is left floating, the device enters autosequencing mode: EN1's rising edge enables the buck first, and the LDO follows after a 5 ms internal delay - ensuring proper rail ordering without external timing circuitry.
What is the minimum input voltage required for the LDO section of the ADP2140ACPZ1812R7?
The LDO input (VIN2) of the ADP2140ACPZ1812R7 accepts voltages from 1.65 V to 5.5 V. This allows direct connection to the 1.8 V buck output, resulting in only 110 mV dropout at full 300 mA load - maximizing efficiency and minimizing thermal dissipation in the LDO.
How does the ADP2140ACPZ1812R7 achieve low output noise on its LDO rail?
The ADP2140ACPZ1812R7 achieves 40 μVrms output noise (10 Hz–100 kHz) at 1.2 V through a combination of low-noise bandgap reference design, optimized error amplifier topology, and high PSRR (65 dB @ 10 kHz), which suppresses coupled noise from the buck switch node when VIN2 is sourced from the buck output.
Is an external feedback resistor network required for the ADP2140ACPZ1812R7?
No - the ADP2140ACPZ1812R7 is a fixed-output variant. Its 1.8 V buck and 1.2 V LDO outputs are internally trimmed and do not require external FB resistors. The FB pin is reserved for adjustable versions and remains unused in this part; it should be left unconnected or tied to AGND per layout guidelines.
ADP2140ACPZ1812R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.8V, 600mA
- Voltage/Current - Output 2:
- 1.2V, 300mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-LFCSP-WD (3x3)
ADP2140ACPZ1812R7 FAQ
1.How can I place an order for ADP2140ACPZ1812R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2140ACPZ1812R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2140ACPZ1812R7 reliable?
The price and inventory of ADP2140ACPZ1812R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2140ACPZ1812R7 is usually 5 days.
3.What payment methods are accepted for ADP2140ACPZ1812R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2140ACPZ1812R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2140ACPZ1812R7?
ADP2140ACPZ1812R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2140ACPZ1812R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2140ACPZ1812R7?
For technical support, including ADP2140ACPZ1812R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2140ACPZ1812R7 requirements.
6.How does Aetrix verify that ADP2140ACPZ1812R7 is sourced from the original manufacturer or authorized distributors?
All ADP2140ACPZ1812R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2140ACPZ1812R7 meets industry standards.
7.What is the process for return or replacement of ADP2140ACPZ1812R7?
All ADP2140ACPZ1812R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2140ACPZ1812R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2140ACPZ1812R7 part is unused and in its original packaging.
Return procedure for ADP2140ACPZ1812R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADP2140ACPZ1812R7 Tags

-
TPS6521905RHBR
Texas Instruments

-
MIC3385YHL-TR
Microchip Technology

-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments

-
A4402KLPTR-T
Allegro MicroSystems

-
BD71847AMWV-E2
ROHM Semiconductor

-
ADP5040ACPZ-1-R7
Analog Devices Inc.

-
LT3048IDC#TRPBF
Analog Devices Inc.

-
ADP5037ACPZ-R7
Analog Devices Inc.

-
XRP7714ILB-F
MaxLinear, Inc.

-
LTC3260EDE#TRPBF
Analog Devices Inc.

-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

