Analog Devices Inc. ADP2140ACPZ2518R7

Overview

ADP2140ACPZ2518R7 from Analog Devices is a dual-output power management IC integrating a 600 mA synchronous buck regulator and a 300 mA low-noise LDO in a single 10-lead 3 mm × 3 mm LFCSP package. It operates from 2.3 V to 5.5 V input, delivers buck output from 1.0 V to 3.3 V and LDO output from 0.8 V to 3.3 V, and supports mobile power rails requiring high PSRR and ultra-low quiescent current - such as baseband processor core and I/O supply sequencing in smartphones.

For engineers reviewing the ADP2140ACPZ2518R7 datasheet, ADP2140ACPZ2518R7 pinout, ADP2140ACPZ2518R7 application, or ADP2140ACPZ2518R7 equivalent, key selection criteria include its 3 MHz switching frequency, 22 μA LDO quiescent current, 65 dB PSRR at 10 kHz, 110 mV dropout at 300 mA, and autosequencing enable logic - all critical for battery-powered portable systems with tight noise and efficiency constraints.

Technical Context

The ADP2140ACPZ2518R7 implements a high-speed current-mode PWM buck controller with variable-frequency PSM mode for light-load efficiency, plus an independent low-dropout linear regulator optimized for split-supply operation (VIN2 ≥ 1.65 V). Its dual-enable architecture supports logic-controlled or autosequencing startup, where EN1 initiates buck activation and EN2 controls LDO enable or defers to buck output.

Power-good monitoring is implemented via an open-drain PG pin asserting high only when both regulated outputs exceed 92% of nominal voltage; internal soft-start limits inrush current, while thermal shutdown (150°C) and current-limit protection (1.1–1.3 A buck, 360–760 mA LDO) ensure robust operation under fault conditions.

Key Specifications

Pinout & Package

ADP2140ACPZ2518R7 uses a 10-lead 3 mm × 3 mm LFCSP package with exposed thermal pad (EP) electrically connected to PGND. The package supports high-density PCB layout and efficient heat dissipation via soldered EP-to-ground-plane connection.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output PMIC applications.

Compared with TPS62745DSSR and MAX8646ETA+T, ADP2140ACPZ2518R7 uniquely combines programmable dual-output regulation, split-supply LDO operation, and sub-25 μA quiescent current - making it optimal for compact, battery-constrained devices needing both efficiency and analog cleanliness.

Availability

ADP2140ACPZ2518R7 is available at Aetrix Electronics and suitable for mobile phones, digital cameras, portable audio devices, and wearable electronics requiring stable component supply across extended production lifecycles.

Supply support for ADP2140ACPZ2518R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP2140ACPZ2518R7 belongs to Analog Devices' Power Management IC portfolio, designed specifically for space- and power-constrained portable electronics requiring high integration, low noise, and intelligent sequencing.

FAQ

What is the recommended input capacitor for ADP2140ACPZ2518R7?

The ADP2140ACPZ2518R7 requires a minimum 10 µF X7R/X5R ceramic input capacitor (CIN) placed close to VIN1 and PGND pins. This value ensures stability across temperature and load, suppresses input ripple, and meets the 7.5 µF minimum specified over −40°C to +125°C. Use low-ESR (<10 mΩ) capacitors and avoid Y5V/Z5U dielectrics due to capacitance loss under DC bias.

Can ADP2140ACPZ2518R7 operate with VIN2 supplied from the buck output?

Yes, ADP2140ACPZ2518R7 supports split-supply operation where VIN2 is connected to VOUT. This configuration leverages the buck's efficiency while using the LDO to clean residual switching noise. For a 1.8 V buck output, VIN2 must be ≥2.1 V (VOUT + 0.3 V) to maintain LDO regulation - confirmed in the datasheet's Recommended Specifications table and Figure 2.

What is the power-good assertion timing for ADP2140ACPZ2518R7?

The ADP2140ACPZ2518R7 asserts PG high after both VOUT and VOUT2 reach ≥92% of their nominal values, with a typical delay of 5 ms in PWM mode. PG remains high until either output falls below 86% of nominal, providing 6% hysteresis. This behavior is verified in the Specifications table (PGRISE/PGFALL) and Figure 41 startup waveform.

How does ADP2140ACPZ2518R7 handle light-load efficiency?

ADP2140ACPZ2518R7 transitions from PWM to pulse-skipping mode (PSM) below ~100 mA load, reducing switching frequency to minimize gate charge losses. In PSM, quiescent current drops to 20 μA for the buck stage, extending battery life in standby. This threshold and behavior are characterized in Figure 9 and specified in Table 1 under "PWM To PSM Threshold".

Is the exposed pad (EP) on ADP2140ACPZ2518R7 electrically connected?

Yes, the exposed pad on ADP2140ACPZ2518R7 is electrically connected to PGND inside the package and must be soldered to a solid ground plane on the PCB. This connection is critical for thermal performance (θJA = 35.3°C/W) and electrical stability, as stated in the Pin Configuration section and Figure 3 note.