Analog Devices Inc. ADP2140ACPZ3325R7

Overview

ADP2140ACPZ3325R7 from Analog Devices is a dual-output power management IC integrating a 600 mA synchronous buck regulator and a 300 mA low-noise LDO in a single 10-lead 3 mm × 3 mm LFCSP package. It operates from 2.3 V to 5.5 V input, delivers 1.0–3.3 V buck output and 0.8–3.3 V LDO output, and supports mobile power sequencing with independent enable pins. It is used in battery-powered portable electronics requiring ultra-low quiescent current (20 μA buck / 22 μA LDO) and high PSRR.

For engineers reviewing the ADP2140ACPZ3325R7 datasheet, ADP2140ACPZ3325R7 pinout, ADP2140ACPZ3325R7 application, or ADP2140ACPZ3325R7 equivalent, key selection criteria include its dual-rail capability, 3 MHz switching frequency, 110 mV dropout at 300 mA, 65 dB PSRR at 10 kHz, and autosequencing support via EN1/EN2 logic control - all critical for compact, low-noise, multi-rail portable designs.

Technical Context

The ADP2140ACPZ3325R7 implements a current-mode PWM buck controller with automatic transition to pulse-skipping mode (PSM) below 100 mA load, reducing quiescent current to 20 μA. Its LDO section features split-supply operation (VIN2 ≥ 1.65 V), enabling direct connection to the buck output to improve system efficiency and reduce thermal dissipation.

Power sequencing is configurable via two logic inputs: EN1 controls buck startup and initiates autosequencing, while EN2 enables the LDO independently or defaults to autosequencing mode. The integrated power-good (PG) open-drain signal asserts only after both outputs stabilize within ±8% of nominal value, with 5 ms delay between buck and LDO outputs in PWM mode.

Key Specifications

Pinout & Package

ADP2140ACPZ3325R7 uses a 10-lead, 0.75 mm pitch, 3 mm × 3 mm LFCSP package with exposed thermal pad electrically connected to PGND. The pad must be soldered to a PCB ground plane for optimal thermal performance (θJA = 35.3°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output PMIC applications.

Compared with TPS62740DRYR and MAX8640YETA+, ADP2140ACPZ3325R7 uniquely combines independent buck+LDO enables, a dedicated PG signal, 65 dB PSRR, and 3 mm × 3 mm footprint - making it the only option that satisfies simultaneous sequencing control, analog noise suppression, and space-constrained portable designs.

Availability

ADP2140ACPZ3325R7 is available at Aetrix Electronics and suitable for mobile phones, digital cameras, portable audio devices, and wearable health monitors requiring stable component supply across extended production lifecycles.

Supply support for ADP2140ACPZ3325R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP2140ACPZ3325R7 belongs to Analog Devices' Power Management portfolio, designed specifically for space- and power-constrained portable electronics requiring high integration, low quiescent current, and robust noise immunity.

FAQ

What is the recommended input capacitor for ADP2140ACPZ3325R7?

The ADP2140ACPZ3325R7 requires a minimum 10 µF X7R/X5R ceramic input capacitor (CIN) placed close to VIN1 and PGND pins. This value ensures stability across temperature and load, meets ripple current rating, and maintains <10 mΩ effective series resistance (ESR) per datasheet Table 2. Using Y5V or Z5U dielectrics is not recommended due to capacitance drift.

Does ADP2140ACPZ3325R7 support independent enable control for buck and LDO outputs?

Yes, ADP2140ACPZ3325R7 supports independent enable control: EN1 directly enables the buck regulator, while EN2 enables the LDO. When EN2 is left unconnected, the device enters autosequencing mode where the LDO powers on only after the buck output reaches regulation - ensuring safe power-up order without external logic.

What is the maximum junction temperature specification for ADP2140ACPZ3325R7?

The ADP2140ACPZ3325R7 has a maximum operating junction temperature of +125°C, with thermal shutdown activating at +150°C (TSSD) and 20°C hysteresis. Its 35.3°C/W θJA (4-layer board) means ambient temperature must be derated under high load; for example, at 600 mA buck + 300 mA LDO, power dissipation exceeds 0.5 W, requiring careful thermal pad layout and airflow consideration.

Can ADP2140ACPZ3325R7's LDO be powered from its own buck output?

Yes, ADP2140ACPZ3325R7's LDO (VIN2) can be directly powered from the buck output (VOUT), provided VOUT ≥ (VOUT2 + 0.3 V). This configuration improves overall system efficiency by avoiding linear dropout losses from a higher input source and reduces thermal stress - a key design advantage confirmed in Figure 2 of the datasheet.

What is the purpose of the exposed thermal pad on ADP2140ACPZ3325R7?

The exposed pad on ADP2140ACPZ3325R7 is electrically connected to PGND inside the package and serves two critical functions: it lowers thermal resistance (reducing θJA from ~60°C/W to 35.3°C/W) and provides a low-inductance ground return path for high-frequency switch currents. Per datasheet Figure 3, it must be soldered to a solid PCB ground plane using ≥6 thermal vias for reliable operation.