Analog Devices Inc. ADP2360ACPZ-5.0-R7
- Part No.:
- ADP2360ACPZ-5.0-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 8-WDFN Exposed Pad, CSP
- Datasheet:
-
ADP2360ACPZ-5.0-R7.pdf
- Description:
- IC REG BUCK 5V 50MA 8LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP2360ACPZ-5.0-R7 from Analog Devices is a high-efficiency, synchronous step-down DC/DC switching regulator optimized for high-input-voltage, low-output-current applications. It operates from 4.5 V to 60 V input, delivers a factory-programmed fixed 5.0 V output at up to 50 mA continuous current, and uses pulse frequency modulation (PFM) in discontinuous conduction mode (DCM) to achieve >87% efficiency at light loads - ideal for powering HART modems and 4–20 mA loop-powered sensors.
For engineers reviewing the ADP2360ACPZ-5.0-R7 datasheet, ADP2360ACPZ-5.0-R7 pinout, ADP2360ACPZ-5.0-R7 application, or ADP2360ACPZ-5.0-R7 equivalent, key selection criteria include its 5.0 V fixed output tolerance (±1%), 12 µA sleep-mode quiescent current, 8-lead 3 mm × 3 mm LFCSP package with exposed thermal pad, and integrated power-good (PG) open-drain output with 4.625 V rising threshold.
Technical Context
The ADP2360ACPZ-5.0-R7 implements a single-pulse PFM control scheme with adjustable peak inductor current limit (IPEAK), enabling optimization of efficiency, ripple, and frequency across varying load conditions. Its internal feedback divider sets VOUT = 5.0 V with ±1% accuracy over temperature and line, eliminating external resistors.
It features precision enable logic (VEN_RISING = 1.0 V, hysteresis = 50 mV), programmable soft start via external capacitor, undervoltage lockout (UVLO rising = 4.4 V), thermal shutdown (TSHDN = 150°C), and 100% duty cycle operation - allowing regulation even when VIN ≈ VOUT. The PG pin provides active-high status indication with 250 mV hysteresis and internal 1.5 kΩ pull-down.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 60 V - supports wide industrial and automotive supply rails without pre-regulation. |
| Output Voltage | Fixed 5.0 V ±1% - factory-trimmed; no external feedback resistors required. |
| Max Continuous Output Current | 50 mA - sufficient for low-power microcontrollers, transceivers, and sensor signal chains. |
| Quiescent Current (Sleep Mode) | 12 µA typical - enables ultra-low-power operation in battery-backed or energy-harvesting systems. |
| Efficiency @ 9 VIN, 10 mA | 87% - achieved via synchronous DCM PFM architecture minimizing switching and conduction losses. |
| Power-Good Threshold | 4.625 V rising, 4.375 V falling - ensures reliable system reset and sequencing in 5 V domains. |
| Shutdown Current | <4 µA - reduces standby power in always-on monitoring nodes. |
| Operating Junction Temp | −40°C to +125°C - qualified for harsh industrial and automotive under-hood environments. |
Pinout & Package
ADP2360ACPZ-5.0-R7 is housed in an 8-lead, 3 mm × 3 mm LFCSP package with exposed EPAD (AGND) for thermal and electrical grounding. The package is RoHS-compliant and rated for JEDEC J-STD-020 reflow.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - EN | Enable input with precision thresholds | Active-high logic; 1.0 V turn-on threshold with 50 mV hysteresis - enables clean power sequencing without external level shifters. |
| 2 - PG | Open-drain power-good output | Indicates stable 5.0 V output; requires external pull-up; sinks current when VOUT is out-of-regulation. |
| 3 - ITH | Peak inductor current programming | Connect resistor to AGND to set IPEAK from 50 mA (open) to 140 mA - tunes efficiency vs. ripple trade-off. |
| 4 - FB | Feedback input (internal divider) | Internally connected to 5.0 V reference; not used in fixed-output variant - simplifies layout and BOM. |
| 5 - SS | Soft-start timing node | Accepts external capacitor to control ramp rate of 5.0 V output - prevents inrush and stabilizes downstream circuitry. |
| 6 - PGND | Power ground return | Low-impedance path for NMOS switch and inductor return - must be tied to solid ground plane under EPAD. |
| 7 - SW | Switch node | Drain connection of internal PMOS/NMOS pair - high dv/dt node requiring tight layout and minimal trace area. |
| 8 - VIN | Main input voltage supply | Accepts 4.5–60 V; requires local 10 µF ceramic capacitor placed adjacent to pin to suppress switching noise. |
| 9 - AGND (EPAD) | Analog ground / thermal pad | Exposed copper pad; must be soldered to PCB ground plane with ≥4 thermal vias - critical for thermal performance and noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| No external compensation required | Stable operation with only CIN, COUT, L1, and optional CSS - reduces design cycle time and component count. |
| 100% duty cycle capability | Maintains regulation down to VIN = VOUT + dropout (≈5.1 V), enabling use in brownout or battery-depletion scenarios. |
| Integrated power-good (PG) flag | Open-drain NMOS rated to 60 V - allows direct interfacing with 3.3 V or 5 V logic without level-shifting components. |
| Adjustable peak current limit (IPEAK) | Programmable from 50 mA to 140 mA via single resistor - enables optimization for efficiency (high IPEAK) or low ripple (low IPEAK). |
| Ultra-low quiescent current | 12 µA in sleep mode - extends battery life in wireless sensor nodes and loop-powered field instruments. |
| Thermal and UVLO protection | Auto-recovery shutdown at 150°C junction temp and VIN < 4.3 V - ensures robust operation in unregulated industrial supplies. |
Applications
| HART Modem Power Supply | 4–20 mA Loop-Powered Sensor |
|---|---|
Use Scenario: Powers HART-compatible communication ICs (e.g., AD5700, TI HART modem chips) within 4–20 mA current loops where available headroom is limited to ~3.5 V at 20 mA. IC Role / Device Role / Timing Role: Primary 5.0 V bias rail generator; regulates from loop-derived supply while maintaining compliance voltage margin. Use Value: Delivers stable 5.0 V at ≤50 mA with 87% efficiency at 9 VIN/10 mA, enabling full-duplex HART communication without violating loop voltage limits. |
Use Scenario: Supplies analog front-end (AFE), ADC, and low-power MCU in two-wire industrial pressure/temperature transmitters. IC Role / Device Role / Timing Role: Isolated auxiliary rail generator; decouples digital subsystem from loop current variations. Use Value: 12 µA sleep current and 4 µA shutdown current minimize loop burden; PG output synchronizes ADC sampling with rail stability. |
| Building Automation Controller | Distributed Industrial Power Node |
Use Scenario: Powers Zigbee/Thread SoCs (e.g., EFR32MG, nRF52840) and environmental sensors in battery- or energy-harvesting–powered smart thermostats. IC Role / Device Role / Timing Role: Efficient 5.0 V step-down converter feeding USB-peripheral–compatible logic rails. Use Value: PFM operation maintains >85% efficiency down to 1 mA load - extending battery life beyond 10 years in duty-cycled deployments. |
Use Scenario: Provides localized 5.0 V supply for PLC I/O modules, valve drivers, or CAN transceivers in distributed control cabinets with 24 V or 48 V backplanes. IC Role / Device Role / Timing Role: Point-of-load regulator; replaces linear regulators to reduce heat buildup in confined enclosures. Use Value: 60 V max input withstands load-dump transients; 125°C junction rating ensures reliability in sealed, fanless enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-VIN, low-IOUT buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM5164QPWPRQ1 | 4.5–65 V input, 100 mA output, constant-on-time (COT) control, 14-pin HTSSOP | Higher current, wider VIN, but larger footprint and 10× higher IQ (100 µA sleep) | Choose LM5164QPWPRQ1 only if >50 mA load or automotive AEC-Q100 qualification is required. |
| TPS54202DRCT | 4.5–28 V input, 2 A output, current-mode PWM, 10-pin WSON | Lower VIN range, much higher current, but significantly higher quiescent current (47 µA) and no PG pin | Choose TPS54202DRCT only for cost-sensitive, non-loop-powered 5 V systems needing >100 mA. |
Compared with LM5164QPWPRQ1 and TPS54202DRCT, ADP2360ACPZ-5.0-R7 offers the lowest quiescent current (12 µA), smallest footprint (3 mm × 3 mm), and integrated PG flag - making it uniquely suited for space-constrained, ultra-low-power 4–20 mA and HART applications where every microamp and square millimeter matters.
Availability
ADP2360ACPZ-5.0-R7 is available at Aetrix Electronics and suitable for HART modem power supplies, 4–20 mA loop-powered sensors, and building automation controllers requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for ADP2360ACPZ-5.0-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The ADP2360ACPZ-5.0-R7 belongs to Analog Devices' high-input-voltage DC/DC regulator product line, designed specifically for reliable, efficient power conversion in space- and power-constrained industrial sensing and process control systems.
FAQ
What is the output voltage tolerance of the ADP2360ACPZ-5.0-R7 over temperature and line?
The ADP2360ACPZ-5.0-R7 delivers a factory-programmed 5.0 V output with guaranteed tolerance of ±1% (4.95 V to 5.05 V) across −40°C to +125°C junction temperature and 4.5 V to 60 V input voltage range, as specified in Table 1 of the Rev. A datasheet under FB Rising Threshold for fixed 5.0 V models.
Does the ADP2360ACPZ-5.0-R7 require external feedback resistors to set the output voltage?
No. The ADP2360ACPZ-5.0-R7 integrates a precision internal resistive divider to set the 5.0 V output; the FB pin is internally connected and not accessible for external configuration. This eliminates BOM items and layout complexity versus adjustable variants like ADP2360ACPZ-R7.
What is the maximum allowable input voltage for the ADP2360ACPZ-5.0-R7, and what protection applies beyond that?
The absolute maximum input voltage for ADP2360ACPZ-5.0-R7 is +61 V (VIN to AGND/PGND), per Table 2. Operation above 60 V violates the recommended operating range and risks permanent damage. The device includes undervoltage lockout (UVLO) but no overvoltage protection - external TVS or clamp circuits are required for transient suppression in 48 V or 60 V systems.
How does the power-good (PG) pin behave during startup and fault conditions for the ADP2360ACPZ-5.0-R7?
During startup, the PG pin remains low (NMOS on) until VOUT reaches 4.625 V (VPG_RISING), then transitions high-impedance (NMOS off). During UVLO, thermal shutdown, or EN deactivation, the internal discharge resistor pulls PG low. The PG pin has 250 mV hysteresis (VPG_FALLING = 4.375 V) to prevent chatter near regulation threshold.
Can the ADP2360ACPZ-5.0-R7 operate with 100% duty cycle, and what are the implications for output current?
Yes. The ADP2360ACPZ-5.0-R7 supports 100% duty cycle operation when VIN ≈ VOUT, maintaining regulation with only PMOS conduction. In this mode, the output current limit approximates IPEAK (set via RITH); for reliable operation, load current must remain below 50% of IPEAK to avoid current limiting when VIN rises above VOUT.
ADP2360ACPZ-5.0-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-WDFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 60V
- Voltage - Output (Min/Fixed):
- 5V
- Voltage - Output (Max):
- -
- Current - Output:
- 50mA
- Frequency - Switching:
- -
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-LFCSP (3x3)
ADP2360ACPZ-5.0-R7 FAQ
1.How can I place an order for ADP2360ACPZ-5.0-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2360ACPZ-5.0-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2360ACPZ-5.0-R7 reliable?
The price and inventory of ADP2360ACPZ-5.0-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2360ACPZ-5.0-R7 is usually 5 days.
3.What payment methods are accepted for ADP2360ACPZ-5.0-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2360ACPZ-5.0-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2360ACPZ-5.0-R7?
ADP2360ACPZ-5.0-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2360ACPZ-5.0-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2360ACPZ-5.0-R7?
For technical support, including ADP2360ACPZ-5.0-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2360ACPZ-5.0-R7 requirements.
6.How does Aetrix verify that ADP2360ACPZ-5.0-R7 is sourced from the original manufacturer or authorized distributors?
All ADP2360ACPZ-5.0-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2360ACPZ-5.0-R7 meets industry standards.
7.What is the process for return or replacement of ADP2360ACPZ-5.0-R7?
All ADP2360ACPZ-5.0-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2360ACPZ-5.0-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2360ACPZ-5.0-R7 part is unused and in its original packaging.
Return procedure for ADP2360ACPZ-5.0-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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