Analog Devices Inc. ADP2380AREZ-R7
- Part No.:
- ADP2380AREZ-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
ADP2380AREZ-R7.pdf
- Description:
- IC REG BUCK ADJ 4A 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:924
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Product details
Overview
ADP2380AREZ-R7 from Analog Devices is a current-mode, synchronous step-down DC-DC regulator integrating a 44 mΩ high-side MOSFET and low-side gate driver. It operates from 4.5 V to 20 V input, delivers up to 4 A continuous output current, features 0.6 V ±1% reference voltage, programmable 250 kHz–1.4 MHz switching frequency, and power-good output. It targets intermediate power rail conversion in communications infrastructure and industrial systems.
For engineers reviewing the ADP2380AREZ-R7 datasheet, ADP2380AREZ-R7 pinout, ADP2380AREZ-R7 application, or ADP2380AREZ-R7 equivalent, key selection considerations include its 16-lead TSSOP_EP package, external compensation capability, startup into precharged output support, 180° out-of-phase synchronization, and integrated thermal shutdown with 150°C trip point.
Technical Context
The ADP2380AREZ-R7 uses fixed-frequency peak current-mode PWM control with internal slope compensation. Its oscillator supports RT-pin programming (250 kHz–1.4 MHz) or external clock synchronization (250 kHz–1.4 MHz) with 180° phase offset, enabling noise-sensitive multi-rail systems.
It integrates an 8 V internal regulator (VREG) for biasing, bootstrap circuitry generating ~5 V between BST and SW, and a dedicated low-side driver (LD) with 20 ns rise/10 ns fall time into 2.2 nF load. Protection includes hiccup-mode OCP, OVP (0.7 V FB threshold), UVLO with programmable threshold via UVLO pin, and thermal shutdown with 25°C hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 20 V - supports wide-input industrial and telecom rails including 5 V, 12 V, and 18 V supplies. |
| Output Current | 4 A continuous - enables single-chip solution for intermediate power rails without external current boosting. |
| Reference Voltage | 0.6 V ±1% over −40°C to +125°C - ensures tight output regulation accuracy across full junction temperature range. |
| Switching Frequency | 250 kHz to 1.4 MHz programmable - allows optimization of size (higher fSW → smaller L/C) vs. efficiency (lower fSW → lower switching loss). |
| High-Side RDS(on) | 44 mΩ typical - reduces conduction loss at high load, critical for >3 A applications at 12 V input. |
| Power-Good Output | Open-drain, 95% rising / 90% falling threshold - provides reliable sequencing signal with built-in 1024-cycle deglitch for stable system power-up. |
| Thermal Shutdown | 150°C trip, 125°C recovery - protects against sustained overload or poor PCB thermal design while enabling automatic restart after cooling. |
Pinout & Package
ADP2380AREZ-R7 is housed in a 16-lead TSSOP_EP (exposed pad) package. The exposed pad must be soldered to a large copper ground plane for thermal dissipation per JEDEC J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVIN (1,2) | Primary power input | Connects to input source and bypass capacitor; dual pins reduce IR drop and improve current handling. |
| UVLO (3) | Undervoltage lockout control | External resistor divider sets turn-on threshold; overrides internal 4.5 V default for custom brown-out behavior. |
| PGOOD (4) | Power-good status indicator | Open-drain output requiring external pull-up; asserts high only after FB reaches 95% of 0.6 V with 1024-cycle delay. |
| EN/SS (7) | Enable and soft-start control | Logic-high (>0.5 V) enables operation; capacitor to GND programs slow soft-start ramp for inrush control. |
| RT (5) | Frequency programming | Resistor to GND sets fSW from 250 kHz to 1.4 MHz; open = 540 kHz, grounded = 290 kHz. |
| SYNC (6) | External clock input | Accepts 250 kHz–1.4 MHz clock; forces 180° phase shift to minimize system EMI coupling. |
| FB (9) | Feedback voltage sense | Monitors resistive divider output; regulates VOUT to 0.6 V × (1 + RTOP/RBOT) with 0.1 µA max bias current. |
| LD (13) | Low-side gate driver output | Drives external N-MOSFET gate; includes break-before-make logic to prevent shoot-through. |
| SW (14,15) | Switch node | Connects to inductor; dual pins reduce parasitic inductance and improve high-frequency switching integrity. |
| BST (16) | Bootstrap supply | Requires 0.1 µF ceramic cap to SW; generates ~5 V gate drive for high-side MOSFET. |
| VREG (12) | Internal 8 V regulator output | Supplies bias for internal circuits and LD driver; requires 1 µF ceramic cap to GND for stability. |
| PGND (11) | Power ground return | Separate from analog GND; connects to source of external low-side MOSFET for clean current return path. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable UVLO | Enables custom input voltage turn-on/off thresholds using external resistor divider on UVLO pin, improving system-level brown-out resilience. |
| Startup into precharged output | Prevents low-side MOSFET activation when VOUT is already charged, avoiding uncontrolled discharge and ensuring safe hot-swap capability. |
| External compensation | Allows full control over loop stability via RC network from COMP to FB, supporting diverse output capacitors and load transient requirements. |
| 180° out-of-phase synchronization | Reduces input ripple current and system-level EMI by aligning switching edges of multiple ADP2380AREZ-R7 regulators in anti-phase configuration. |
| Hiccup-mode overcurrent protection | Enters 4096-cycle shutdown-and-retry cycle upon repeated current-limit faults, preventing thermal runaway while enabling automatic recovery if fault clears. |
Applications
| Communications Infrastructure | Industrial Instrumentation |
|---|---|
Use Scenario: Powering FPGA I/O banks and transceiver cores in 5G base station remote radio units (RRUs). IC Role / Device Role / Timing Role: Primary intermediate buck converter delivering 1.2 V/3.3 V rails from 12 V backplane supply. Use Value: 4 A output capacity and 0.6 V reference enable precise low-voltage rail generation; synchronization minimizes spectral interference with RF front-end. | Use Scenario: Supplying isolated ADC/DAC signal chains and microcontroller subsystems in programmable logic controllers (PLCs). IC Role / Device Role / Timing Role: Point-of-load regulator converting 24 V industrial bus to 5 V/3.3 V for mixed-signal precision circuits. Use Value: Wide 4.5–20 V input range accommodates 24 V nominal with brown-out margin; thermal shutdown ensures reliability in enclosed enclosures. |
| Networking & Servers | Healthcare Equipment |
Use Scenario: Generating 1.8 V core voltage for Ethernet switch ASICs in enterprise switches. IC Role / Device Role / Timing Role: High-efficiency synchronous buck providing stable core rail with fast transient response. Use Value: 44 mΩ high-side RDS(on) and current-mode control deliver >90% efficiency at 4 A; PGOOD enables safe ASIC reset sequencing. | Use Scenario: Powering imaging sensor interfaces and real-time processing modules in portable ultrasound devices. IC Role / Device Role / Timing Role: Low-noise, compact buck regulator supplying regulated 1.2 V and 3.3 V rails from Li-ion battery or AC adapter. Use Value: Programmable soft start prevents inrush-induced voltage sag on shared battery rail; external compensation maintains stability with ceramic output caps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LM5164QDRCRQ1 | Automotive-grade (AEC-Q100), 3.5 A max, 4.5–65 V input, integrated high/low-side FETs, no external low-side driver required. | Designed for automotive infotainment and ADAS; lacks programmable UVLO and 180° sync; higher VIN range trades off for lower IOUT. | Select LM5164QDRCRQ1 only for automotive environments requiring AEC-Q100 qualification and wider input range; not drop-in due to different pinout and control architecture. |
| TPS544B25RVR | 4 A, 4.5–18 V input, integrated FETs, PMBus interface, 2.5 mΩ high-side RDS(on), no external low-side driver needed. | Targeted at server VR13/IMVP8 compliance; adds digital telemetry and margining; higher cost and complexity for non-PMBus systems. | Choose TPS544B25RVR when digital monitoring, margining, or tighter output tolerance (<±0.5%) is required; ADP2380AREZ-R7 offers simpler analog control and lower BOM count. |
Compared with LM5164QDRCRQ1 and TPS544B25RVR, ADP2380AREZ-R7 provides a balanced analog solution with external low-side driver flexibility, robust 4 A capability at 20 V max input, and proven thermal performance in industrial ambient conditions-without automotive qualification overhead or digital interface complexity.
Availability
ADP2380AREZ-R7 is available at Aetrix Electronics and suitable for communications infrastructure, industrial instrumentation, and healthcare equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for ADP2380AREZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision, industrial, communications, and automotive markets.
The ADP2380AREZ-R7 belongs to Analog Devices' high-efficiency power management product line, designed specifically for intermediate bus conversion in space-constrained, thermally demanding applications where flexibility in frequency, sequencing, and protection is critical.
FAQ
What is the maximum input voltage rating for ADP2380AREZ-R7?
The ADP2380AREZ-R7 has an absolute maximum PVIN rating of +22 V, but its specified operational input voltage range is 4.5 V to 20 V. Operating continuously at 20 V is supported across the full −40°C to +125°C junction temperature range, with derating advised above this level per Absolute Maximum Ratings table.
Does ADP2380AREZ-R7 integrate both high-side and low-side power switches?
No, ADP2380AREZ-R7 integrates only the 44 mΩ high-side N-channel MOSFET. It provides a dedicated low-side gate driver (LD pin) to control an external N-channel MOSFET, enabling optimized selection of low-RDS(on) devices for specific efficiency and thermal requirements.
Can ADP2380AREZ-R7 be synchronized to an external clock, and what is the phase relationship?
Yes, ADP2380AREZ-R7 accepts an external clock on the SYNC pin across 250 kHz to 1.4 MHz. During synchronization, its switching rising edge is locked 180° out of phase with the external clock's rising edge-enabling interleaved operation to reduce input ripple and system EMI.
What is the purpose of the UVLO pin on ADP2380AREZ-R7, and how is it configured?
ADP2380AREZ-R7's UVLO pin allows customization of the input undervoltage lockout threshold using an external resistor divider from PVIN to GND. This overrides the internal 4.5 V default, enabling precise brown-out behavior tailored to system-level power sequencing and hold-up time requirements.
How does ADP2380AREZ-R7 handle startup when the output is already precharged?
ADP2380AREZ-R7 detects precharged output conditions during startup and disables the low-side MOSFET until the internal soft-start voltage exceeds the FB pin voltage. This prevents uncontrolled discharge of the output capacitor and ensures safe hot-swap operation without damaging downstream components.
ADP2380AREZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 20V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 18V
- Current - Output:
- 4A
- Frequency - Switching:
- 250kHz ~ 1.4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP-EP
ADP2380AREZ-R7 FAQ
1.How can I place an order for ADP2380AREZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP2380AREZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP2380AREZ-R7 reliable?
The price and inventory of ADP2380AREZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP2380AREZ-R7 is usually 5 days.
3.What payment methods are accepted for ADP2380AREZ-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP2380AREZ-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP2380AREZ-R7?
ADP2380AREZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP2380AREZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP2380AREZ-R7?
For technical support, including ADP2380AREZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP2380AREZ-R7 requirements.
6.How does Aetrix verify that ADP2380AREZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADP2380AREZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP2380AREZ-R7 meets industry standards.
7.What is the process for return or replacement of ADP2380AREZ-R7?
All ADP2380AREZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP2380AREZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP2380AREZ-R7 part is unused and in its original packaging.
Return procedure for ADP2380AREZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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