Analog Devices Inc. ADP2381AREZ

Overview

ADP2381 from Analog Devices is a synchronous step-down DC-DC regulator with integrated 44 mΩ high-side MOSFET and low-side gate driver, supporting 4.5 V to 20 V input, 0.6 V ±1% reference voltage, 6 A continuous output current, and programmable 250 kHz–1.4 MHz switching frequency. It delivers stable intermediate power rails in networking servers and industrial instrumentation.

For engineers reviewing the ADP2381 datasheet, ADP2381 pinout, ADP2381 application, or ADP2381 equivalent, key selection considerations include its external compensation capability, 180° out-of-phase synchronization support, programmable UVLO, power-good output with 1024-cycle deglitching, and startup into precharged output functionality.

Technical Context

The ADP2381 employs fixed-frequency peak current-mode PWM control with internal slope compensation and break-before-make low-side driver logic to prevent cross-conduction. Its oscillator supports RT-resistor programming (210–690 kHz default) or external SYNC clock locking (250 kHz–1.4 MHz) with 180° phase offset.

It integrates an 8 V internal regulator (VREG) with 7.6–8.4 V output and 65–135 mA current limit, bootstrap circuitry generating 4.5–5.7 V between BST and SW, and comprehensive protection including OVP (0.7 V FB threshold), hiccup-mode OCP, thermal shutdown at 150°C with 25°C hysteresis, and negative current-limit detection at 20 mV.

Key Specifications

Pinout & Package

ADP2381 is housed in a thermally enhanced 16-lead TSSOP_EP package with exposed pad soldered to PCB ground plane for optimal thermal dissipation (θ_JA = 39.48°C/W on 4-layer JEDEC board).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down regulator applications.

Compared with LM5143AQPWPRQ1 and TPS546B24RVFT, the ADP2381 uniquely combines external low-side driver control, 180° synchronization, and startup into precharged outputs-making it optimal for high-density, multi-rail analog/RF systems where timing coordination and fault resilience are critical.

Availability

ADP2381 is available at Aetrix Electronics and suitable for communication infrastructure, industrial instrumentation, and healthcare equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for ADP2381 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision, industrial, communications, and automotive markets.

The ADP2381 belongs to Analog Devices' high-efficiency power management product line, engineered specifically for intermediate bus conversion and point-of-load regulation in space-constrained, thermally demanding applications like networking gear and medical imaging systems.

FAQ

What is the minimum output voltage achievable with ADP2381 at 12 V input and 500 kHz switching frequency?

The ADP2381 minimum output voltage is constrained by its 120 ns minimum on-time. At 12 V input and 500 kHz, V_{OUT_MIN} ≈ 12 V × (120 ns × 500 kHz) = 0.72 V, assuming ideal MOSFETs and zero inductor DCR. The ADP2381 datasheet confirms operation down to 0.6 V, enabled by internal compensation and current-mode control tolerating duty cycles below this theoretical limit. Real-world minimum is validated at 0.6 V across temperature.

Does ADP2381 require an external low-side MOSFET, and what are the key selection criteria?

Yes, ADP2381 requires an external low-side N-channel MOSFET driven by the LD pin. Key selection criteria include R_DS(on) ≤ 10 mΩ (to maintain efficiency), Q_g compatible with LD's 4–6 Ω sourcing / 2–3.5 Ω sinking resistance, and voltage rating ≥ input voltage. The datasheet recommends FDS6298 as a validated option; gate drive timing must respect the LD's 10–20 ns rise/fall times under 2.2 nF load.

How does the ADP2381 handle startup when the output capacitor is already charged to the target voltage?

The ADP2381 supports startup into a precharged output by disabling the low-side MOSFET until the internal soft-start voltage exceeds the FB pin voltage. This prevents reverse current flow from the output capacitor through the low-side FET, avoiding uncontrolled discharge and potential damage. The EN/SS pin controls this behavior, and the feature is active regardless of whether internal or external soft start is used.

What is the purpose of the UVLO pin on ADP2381, and how is it configured?

The UVLO pin on ADP2381 allows customization of the input undervoltage lockout threshold beyond the internal 4.3 V (rising) / 3.7 V (falling) default. It accepts an external resistor divider from PVIN to GND, overriding the internal 320 kΩ/125 kΩ divider. This enables precise brownout protection tailored to specific input supply characteristics, such as battery voltage sag or unregulated adapter droop, improving system reliability in variable-input environments.

Can ADP2381 synchronize to an external clock while operating at 250 kHz, and what are the timing requirements?

Yes, ADP2381 supports external synchronization across its full 250 kHz–1.4 MHz range, including 250 kHz. The SYNC pin requires a clean CMOS clock with minimum pulse width ≥100 ns and minimum off-time ≥100 ns. During sync, the internal oscillator must be programmed via the RT pin to run within 90–110% of the external clock frequency to ensure stable locking. The ADP2381 then aligns its switching edge 180° out of phase with the external clock's rising edge.