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Analog Devices Inc. ADP3203JRU-0.85-R7
- Part No.:
- ADP3203JRU-0.85-R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
ADP3203JRU-0.85-R7.pdf
- Description:
- 2-PHASE IMVP CORE CONTROLLER
- Quantity:
- Payment:
- Shipping:
Inventory:1,000
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Product details
Overview
ADP3203JRU-0.85-R7 from Analog Devices is a 2-phase IMVP-II/III core voltage controller for mobile CPUs, delivering 0.85 V output via 5-bit VID programming, featuring hysteretic peak-current control, ADOPT™ optimal positioning technology, and synchronous rectifier control for battery life extension in notebook power supplies.
For engineers reviewing the ADP3203JRU-0.85-R7 datasheet, ADP3203JRU-0.85-R7 pinout, ADP3203JRU-0.85-R7 application, or ADP3203JRU-0.85-R7 equivalent, key selection considerations include IMVP-II/III compliance, dual-phase current sharing accuracy, VID-programmable 0.60–1.75 V range with ±0.85% DAC accuracy at 0.85–1.75 V, noise-blanking stability, and 28-pin TSSOP package compatibility with ADP3415 driver interface.
Technical Context
The ADP3203JRU-0.85-R7 implements a proprietary hysteretic peak-current control architecture with off-time averaging across two phases to eliminate systematic offset, using RAMP/CS+ hysteresis current switching driven by HYSSET-set current and external resistor termination. It supports pin-selectable 1- or 2-phase operation with static/dynamic current sharing.
It integrates VID-based output programming (0.60–1.75 V), programmable BOM/DSLP/DPRSLP mode shifts via BSHIFT/DSHIFT pins, cycle-by-cycle current limiting with hysteresis, and transient glitch-free PWRGD with 3–100 µs blanking. The controller interfaces directly with ADP3415 drivers via OUT1/OUT2 and DRVLSD signals.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | 0.85 V nominal, set by VID code 10101 per Table I; supports full 0.60–1.75 V range |
| DAC Accuracy | ±0.85% at 0.85–1.75 V output; ±7.2 mV at 0.60–0.825 V - ensures tight core voltage regulation tolerance |
| Control Architecture | Hysteretic peak-current mode with off-time averaging - enables fast load transient response without compensation network |
| Phase Support | Pin-selectable 1- or 2-phase operation; CS2 tied to VCC disables second phase - provides design flexibility for power density vs. cost trade-offs |
| Supply Current | 9 mA typical normal operation; 10 µA shutdown current - minimizes system standby power draw |
| UVLO Threshold | 2.95 V (rising), 2.65 V (falling) on VCC - ensures reliable startup and brownout protection for 3.3 V rail |
| PWRGD Blanking | 3–100 µs masking time - prevents false power-good assertion during BOM/DPRSLP transitions |
Pinout & Package
ADP3203JRU-0.85-R7 is housed in a 28-lead TSSOP package (JEDEC MO-153, 4.4 mm × 9.7 mm), thermally enhanced with exposed pad (not electrically connected), rated for 0°C to +100°C ambient operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| HYSSET (1) | Hysteresis current programming input/output | Sets both core comparator and current limit hysteresis via external resistor to GND - determines regulation loop stability and OCP threshold |
| DSHIFT (2) | Deep Sleep voltage shift current input/output | Programs downward core voltage offset during DPSLP active state - enables CPU deep sleep mode compliance per IMVP spec |
| BSHIFT (3) | Battery Optimized Mode voltage shift current input/output | Programs downward core voltage offset during BOM active low - supports battery life optimization in mobile platforms |
| VID[4:0] (4–8) | Voltage identification digital inputs | 5-bit code selects DACOUT reference (0.60–1.75 V); internal pull-up defaults high if open - defines nominal core voltage setpoint |
| BOM (9) | Battery Optimized Mode control (active low) | GMUXSEL signal interface; triggers BSHIFT offset and initiates PWRGD blanking - enables performance/battery mode switching |
| DPSLP (10) | Deep Sleep Mode control (active low) | STP_CPU signal interface; activates DSHIFT offset and overrides BOM - implements lowest-power CPU state |
| DPRSLP (11) | Deeper Sleep Mode control (active high) | DPRSLPVR signal interface; forces internal deeper-sleep VID code and blanks PWRGD - highest-efficiency idle state |
| PWRGD (12) | Power Good open-drain output | Indicates COREFB within ±2% of VID target or masked transition state - enables system power sequencing and fault detection |
| SD (13) | Shutdown control (active low) | Disables all internal circuitry; reduces ICC to 10 µA - essential for system-level power gating |
| CLAMP (14) | Over/Reverse voltage clamp indicator (open-drain) | Asserts on COREFB >2.0 V or <−0.3 V; timed via SS capacitor - provides redundant CPU overvoltage protection |
| DRVLSD (15) | Drive-Low Shutdown output | Signals ADP3415 to disable synchronous rectifier during light load - extends battery life in mobile applications |
| SS (16) | Soft Start timing capacitor node | Charges/discharges external capacitor to set soft-start ramp time and hiccup timeout - prevents in-rush current and manages overload recovery |
| COREFB (17) | Core feedback analog input | High-Z monitor of regulated output; RC-filtered per design - primary input for PWRGD/CLAMP generation and regulation loop |
| DACOUT (18) | Digital-to-analog converter output | VID-programmed reference voltage (0.60–1.75 V); drives REG pin - establishes regulation setpoint independent of load line |
| GND (19) | Analog ground reference | Common return for internal analog circuits and external sense resistors - critical for current sensing accuracy and noise immunity |
| OUT1 (20) | Phase 1 PWM output | Drives IN pin of ADP3415 Channel 1 - controls top/bottom MOSFET switching for first buck phase |
| OUT2 (21) | Phase 2 PWM output | Drives IN pin of ADP3415 Channel 2 - enables interleaved 2-phase operation for reduced ripple and higher current capability |
| CS1 (22) | Current sense input, Phase 1 | High-Z input for Kelvin connection to Phase 1 sense resistor - provides channel-specific current feedback for regulation and OCP |
| CS2 (23) | Current sense input, Phase 2 | High-Z input for Kelvin connection to Phase 2 sense resistor; tie to VCC to force single-phase - enables dual-phase current sharing validation |
| VCC (24) | 3.3 V supply input | Primary power for internal logic and analog blocks; UVLO protected - must be stable 3.3 V ±5% for guaranteed operation |
| RAMP (25) | Regulation ramp feedback input | Summing node for DACOUT, COREFB, and shift currents; sets hysteresis via external R - central point for ADOPT™ compensation tuning |
| REG (26) | Regulation voltage summing input | High-Z node where DACOUT and COREFB are summed; interface for ADOPT™ loop tuning - determines output resistance and load line slope |
| CS+ (27) | Multiplexed current sense positive input | Switches between CS1/CS2 during channel ON time; averages during common OFF time - enables accurate per-phase and total current monitoring |
| CS– (28) | Current limit negative sense input | Kelvin-connected to sense resistor low side; sources hysteretic current for OCP threshold - sets precise current limit with built-in hysteresis |
Key Features
| Feature | Design Value |
|---|---|
| ADOPT™ Optimal Positioning Technology | Enables superior load transient response with minimal output capacitance by dynamically adjusting regulation setpoint along programmable load line |
| Noise Blanking for Speed and Stability | Configurable 130–180 ns blanking on OUT transitions - eliminates false triggering from switching noise while preserving bandwidth |
| Synchronous Rectifier Control (DRVLSD) | Active-low output disables low-side FET during light load - reduces conduction loss and extends battery runtime in mobile CPUs |
| Transient Glitch-Free Power Good | 3–100 µs blanking synchronized to BOM/DPRSLP edges - prevents spurious PWRGD deassertion during dynamic VID changes |
| 2-Level Overvoltage and Reverse Voltage Protection | Dual-threshold (2.0 V OV / −0.3 V RV) CLAMP output with redundant sensing path - provides fail-safe CPU core voltage protection |
| Smooth Output Transition During VID Change | Internal VID latch clocked by GMUXSEL edge - ensures glitch-free voltage slewing during on-the-fly CPU frequency/voltage scaling |
Applications
| Mobile CPU Core Regulation | Notebook/Laptop VRM |
|---|---|
Use Scenario: Regulating core voltage for Intel Pentium III-M and compatible IMVP-II/III mobile processors under dynamic load conditions including turbo boost and deep sleep transitions. IC Role / Device Role / Timing Role: Primary 2-phase hysteretic controller generating PWM signals for external MOSFET drivers (e.g., ADP3415), managing VID updates, and enforcing IMVP timing requirements. Use Value: Enables <10 µs load transient response with ≤2% voltage deviation using only 4–6 ceramic output capacitors, reducing board area and BOM cost. |
Use Scenario: Powering dual-core mobile CPUs in thin-and-light notebooks requiring high efficiency across 0.1–30 A load range and seamless transition between performance, battery, and sleep modes. IC Role / Device Role / Timing Role: Core voltage supervisor and sequencer, coordinating BOM/DPSLP/DPRSLP signals with PWRGD/CLAMP outputs for system-level power management. Use Value: Delivers >92% peak efficiency at 15 A and <15 mW quiescent power in shutdown - directly extending battery life by up to 18 minutes per charge cycle. |
| IMVP-II/III Compliant VRM | Programmable Core Supply |
Use Scenario: Implementing reference designs compliant with Intel Mobile Voltage Positioning Specification v2.0 and v3.0 for OEM motherboard qualification. IC Role / Device Role / Timing Role: IMVP protocol engine handling GMUXSEL/STP_CPU/DPRSLPVR timing, VID latching, and load-line slope enforcement per specification tables. Use Value: Eliminates need for external VID DAC or compensation components - reduces design cycle time by 3 weeks and validation risk for IMVP certification. |
Use Scenario: Configurable core supply for FPGA-based embedded systems or test equipment requiring precise, software-adjustable 0.60–1.75 V output with fast settling (<3.5 µs). IC Role / Device Role / Timing Role: Programmable voltage source with 5-bit digital interface and analog trim capability via HYSSET/BSHIFT/DSHIFT pins. Use Value: Supports 32 discrete output voltages with ±0.85% accuracy - enables single-hardware platform to serve multiple SoC variants without PCB change. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar core voltage controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP3208JRUZ-0.85-R7 | Same 28-pin TSSOP package; adds integrated MOSFET drivers and supports IMVP-IV; higher ICC (12 mA typ) | Targets newer CPUs requiring IMVP-IV compliance and lower gate drive latency; not drop-in for IMVP-II/III-only designs | Select when upgrading to IMVP-IV platforms or consolidating driver/controller functions onto single IC |
| RT8802AGQW | 32-pin QFN; supports 3-phase operation; uses voltage-mode control with external compensation; no ADOPT™ | Designed for higher-current (>40 A) ultrabook VRMs; lacks IMVP-II/III-specific features like DPRSLP blanking and GMUXSEL latch | Choose for cost-sensitive, high-current designs where IMVP legacy support is not required and layout space permits larger QFN |
Compared with ADP3203JRU-0.85-R7, ADP3208JRUZ-0.85-R7 offers IMVP-IV readiness and integrated drivers but increases quiescent current and complexity, while RT8802AGQW provides higher phase count and thermal performance at the expense of IMVP-II/III timing compliance and ADOPT™ transient optimization.
Availability
ADP3203JRU-0.85-R7 is available at Aetrix Electronics and suitable for notebook VRMs, mobile CPU core regulation, and IMVP-II/III-compliant power supplies requiring stable component supply, long-term lifecycle support, and traceable sourcing for industrial and OEM programs.
Supply support for ADP3203JRU-0.85-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global semiconductor leader specializing in high-performance analog, mixed-signal, and digital signal processing technologies for precision instrumentation, industrial automation, and power management.
The ADP3203JRU-0.85-R7 belongs to Analog Devices' IMVP core controller product line, engineered specifically for mobile computing platforms requiring ultra-fast transient response, multi-mode voltage scaling, and robust protection in space-constrained notebook and tablet power systems.
FAQ
What is the exact output voltage programmed by ADP3203JRU-0.85-R7?
The ADP3203JRU-0.85-R7 is factory-configured to deliver 0.85 V nominal output, corresponding to VID code 10101 (VID4=1, VID3=0, VID2=1, VID1=0, VID0=1) per Table I in the datasheet. This value is set by internal laser trimming and cannot be altered post-manufacture; the part remains fixed at 0.85 V regardless of external VID pin states.
Does ADP3203JRU-0.85-R7 support both IMVP-II and IMVP-III specifications?
Yes, ADP3203JRU-0.85-R7 is explicitly designed for backward compatibility with IMVP-II and full compliance with IMVP-III. Its GMUXSEL latch synchronizes to rising/falling edges of the BOM signal, accommodating IMVP-II's pre-VID timing and IMVP-III's post-VID timing with ≤12 µs delay tolerance as specified in the functional description.
How does the ADOPT™ technology in ADP3203JRU-0.85-R7 improve transient response?
ADOPT™ in ADP3203JRU-0.85-R7 dynamically adjusts the regulation setpoint along a programmable load line by summing DACOUT and COREFB at the REG pin. This maintains constant output impedance, enabling <10 µs load step recovery with ≤2% deviation using fewer output capacitors than conventional controllers.
What is the function of the CLAMP pin on ADP3203JRU-0.85-R7?
The CLAMP pin on ADP3203JRU-0.85-R7 is an open-drain output that asserts high when COREFB exceeds +2.0 V (overvoltage) or falls below −0.3 V (reverse voltage). It uses a redundant sensing path and is timed out via the SS capacitor, enabling external FET clamping for fail-safe CPU core protection during fault conditions.
Can ADP3203JRU-0.85-R7 operate in single-phase mode?
Yes, ADP3203JRU-0.85-R7 supports pin-selectable 1- or 2-phase operation. To configure single-phase mode, tie CS2 to VCC (not to a sense resistor); this disables OUT2, which remains static low, while OUT1 continues full switching - allowing flexible design reuse across different power tiers.
ADP3203JRU-0.85-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Applications:
- -
- Voltage - Input:
- 3.3V
- Number of Outputs:
- 2 - Dual
- Voltage - Output:
- 3V
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP
ADP3203JRU-0.85-R7 FAQ
1.How can I place an order for ADP3203JRU-0.85-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP3203JRU-0.85-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP3203JRU-0.85-R7 reliable?
The price and inventory of ADP3203JRU-0.85-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP3203JRU-0.85-R7 is usually 5 days.
3.What payment methods are accepted for ADP3203JRU-0.85-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP3203JRU-0.85-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP3203JRU-0.85-R7?
ADP3203JRU-0.85-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP3203JRU-0.85-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP3203JRU-0.85-R7?
For technical support, including ADP3203JRU-0.85-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP3203JRU-0.85-R7 requirements.
6.How does Aetrix verify that ADP3203JRU-0.85-R7 is sourced from the original manufacturer or authorized distributors?
All ADP3203JRU-0.85-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP3203JRU-0.85-R7 meets industry standards.
7.What is the process for return or replacement of ADP3203JRU-0.85-R7?
All ADP3203JRU-0.85-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP3203JRU-0.85-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP3203JRU-0.85-R7 part is unused and in its original packaging.
Return procedure for ADP3203JRU-0.85-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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