Analog Devices Inc. ADP3421JRU-REEL

Overview

ADP3421JRU-REEL from Analog Devices is a hysteretic buck converter controller with dual integrated LDO controllers for mobile CPU core, I/O, and clock rail regulation. It features 5-bit VID-programmable output (0.925 V to 2.000 V), active voltage positioning, programmable current limit, and 15 ns core comparator propagation delay. It interfaces directly with the ADP3410 dual MOSFET driver in Geyserville-enabled notebook power supplies.

For engineers reviewing the ADP3421JRU-REEL datasheet, ADP3421JRU-REEL pinout, ADP3421JRU-REEL application, or ADP3421JRU-REEL equivalent, key selection criteria include VID-programmable core voltage accuracy (±0.85%), hysteretic control architecture for fast transient response, integrated soft-start timers for core and linear regulators, and support for Intel Mobile Voltage Positioning compliance in battery-powered CPU systems.

Technical Context

The ADP3421JRU-REEL implements a proprietary ripple-regulator topology using switched hysteresis current at the RAMP pin, with VHYS and CLSET pins setting hysteresis and current limit thresholds via external resistors. Its core control loop operates without error amplifiers, relying on direct DACOUT-to-REG summing and RAMP-based negative feedback for voltage positioning.

It integrates three independent regulation subsystems: a main hysteretic buck controller (CORE, OUT, DACOUT, REG, RAMP), a 2.5 V CLK LDO controller (CLKDRV/CLKFB), and a 1.5 V I/O LDO controller (IODRV/IOFB), each with dedicated soft-start timing (SSC/SSL) and level-translated enable logic (LTI/LTO/LTB).

Key Specifications

Pinout & Package

TSSOP-28 (RU-28) package with 0.65 mm pitch, thermally enhanced for high-density notebook PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail CPU power controller applications.

Compared with ISL6225CRZ and TPS51020PWR, the ADP3421JRU-REEL uniquely combines hysteretic core control, dual LDO drivers, and level translation in one TSSOP-28 package - enabling minimal-component, Geyserville-compliant CPU power solutions below 15 A core current.

Availability

ADP3421JRU-REEL is available at Aetrix Electronics and suitable for notebook/laptop power supplies, Geyserville-enabled mobile CPU core DC-DC converters, and programmable multi-rail power management systems requiring stable component supply and long-term lifecycle support.

Supply support for ADP3421JRU-REEL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP3421JRU-REEL belongs to Analog Devices' mobile CPU power controller product line, designed specifically to meet Intel's Geyserville voltage positioning requirements and reduce total solution cost in battery-powered computing platforms.

FAQ

What is the primary function of the ADP3421JRU-REEL in a mobile CPU power system?

The ADP3421JRU-REEL serves as a single-chip power controller for Intel mobile CPUs, integrating a hysteretic buck controller for the core rail, two linear regulator controllers for 2.5 V clock and 1.5 V I/O rails, and a level translator. It implements active voltage positioning per Intel Geyserville specifications and interfaces directly with the ADP3410 MOSFET driver. The ADP3421JRU-REEL enables minimal-output-capacitor designs while ensuring fast transient response and precise VID-programmed core voltage regulation.

How does the ADP3421JRU-REEL achieve active voltage positioning without an error amplifier?

The ADP3421JRU-REEL achieves active voltage positioning through its proprietary RAMP/REG feedback architecture: the DACOUT voltage and core output voltage are summed at the REG pin, while the RAMP pin receives inductor-side feedback with hysteresis set by VHYS. This creates a gain-controlled droop characteristic that dynamically lowers core voltage under load - reducing CPU power dissipation and capacitor requirements. Unlike passive droop methods, this loop-gain-based approach avoids power loss across a series resistor. The ADP3421JRU-REEL implements this entirely without external op-amps or compensation components.

Can the ADP3421JRU-REEL be used with non-Intel processors or fixed-voltage applications?

Yes, the ADP3421JRU-REEL supports fixed-voltage operation by tying the VID inputs to static logic levels per Table I in the datasheet, enabling use with non-Intel processors or custom voltage requirements. Its hysteretic control architecture, programmable current limit, and independent soft-start timers remain fully functional regardless of VID source. However, Intel-specific features like Geyserville-compliant voltage positioning timing and PWRGD latency handling are optimized for Pentium III mobile CPUs. For non-Intel use, verify core voltage accuracy (±0.85%) and transient response meet target processor specifications. The ADP3421JRU-REEL retains full functionality in fixed-voltage mode.

What are the critical external components required for basic ADP3421JRU-REEL operation?

Essential external components for the ADP3421JRU-REEL include: (1) VHYS and CLSET resistors to ground for hysteresis and current limit programming; (2) SSC and SSL timing capacitors for core and LDO soft-start; (3) RAMP termination resistor for hysteretic loop stability; (4) external PNP transistors (e.g., ZFT788B) driven by CLKDRV and IODRV for 2.5 V and 1.5 V LDO outputs; and (5) ADP3410 dual MOSFET driver for core buck stage. The ADP3421JRU-REEL requires no external error amplifier, compensation network, or power-good monitoring IC - all functions are integrated.

Does the ADP3421JRU-REEL support power sequencing between core, I/O, and clock rails?

Yes, the ADP3421JRU-REEL provides explicit power sequencing control via independent soft-start timers: SSC governs core rail ramp-up, while SSL controls both 2.5 V clock and 1.5 V I/O LDOs. By selecting different capacitor values on SSC and SSL, designers can stagger startup - e.g., delay I/O and clock rails until core voltage stabilizes - ensuring proper CPU initialization. The PWRGD output asserts only after all three rails meet regulation criteria, providing a single system-ready signal. This eliminates need for external sequencers. The ADP3421JRU-REEL's integrated sequencing reduces BOM count and improves startup reliability in notebook platforms.