onsemi ADP4000JCPZ-REEL
- Part No.:
- ADP4000JCPZ-REEL
- Manufacturer:
- onsemi
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad, CSP
- Datasheet:
-
ADP4000JCPZ-REEL.pdf
- Description:
- IC REG CONV VR11 6OUT 48LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:1,541
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Product details
Overview
ADP4000JCPZ-REEL from onsemi is a 6-phase synchronous buck controller IC with I²C interface, VR11.1-compliant voltage regulation, programmable 0.375–1.8 V output, active current balancing across all phases, and PSI power-saving mode support. It drives external MOSFET drivers (e.g., ADP3121) in high-current CPU core power delivery for servers and desktop PCs.
For engineers reviewing the ADP4000JCPZ-REEL datasheet, pinout, applications, or equivalent options, key selection criteria include phase programmability (1–6), I²C-configurable load line and VID offset, differential remote sensing accuracy (±7 mV), and integrated current measurement via CSREF/CSSUM architecture.
Technical Context
The ADP4000JCPZ-REEL implements a digitally programmable multiphase PWM controller with Fast-Enhanced PWM FlexMode and TRDET-based transient response optimization. Its I²C interface enables real-time readback of CPU voltage, current, and fault status, plus dynamic adjustment of voltage offset, phase count, and load line parameters.
It integrates a precision 8-bit ADC for TTSENSE thermistor monitoring, a dedicated current-sense amplifier with programmable gain (via CSCOMP/CSSUM), and independent per-phase current balance circuitry referenced to SWx pins. The device supports on-the-fly VID code changes and PSI-triggered phase shedding without interrupting regulation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage Range | 0.375 V to 1.8 V programmable via VID0–VID7 DAC; enables precise CPU core rail tuning per VR11.1 spec. |
| Phase Configuration | Selectable 1-, 2-, 3-, 4-, 5-, or 6-phase operation via PWMx pin strapping; allows scalable design from low-power to >200 A systems. |
| I²C Interface | Standard-mode (400 kHz) bidirectional interface for full configuration, telemetry (voltage/current/power), and fault logging. |
| Differential Sensing Accuracy | ±7 mV over full temperature and load range; ensures tight regulation at CPU remote sense point using FB/FBRTN inputs. |
| Current Sensing Architecture | CSREF/CSSUM/CSCOMP-based amplifier with external gain setting; supports DCR, resistor, or thermistor-coupled inductor sensing. |
| PSI Support | Active power-state indicator input enabling automatic phase reduction at light loads; reduces system quiescent power without software intervention. |
| Thermal Monitoring | TTSENSE input with NTC thermistor interface and VRHOT open-drain alert; enables closed-loop thermal throttling coordination with CPU. |
Pinout & Package
LFCSP-48 (7 mm × 7 mm, Case 932AD), Pb-free, exposed pad for thermal dissipation. Pin 1 marked with dot; top-side marking includes "ADP4000", "JCPZ", date code, and country of origin.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ALERT (1) | Fault alert output | Open-drain signal asserting low on programmable overvoltage, undervoltage, or crowbar event; requires external pull-up. |
| FAULT (2) | System fault indicator | Open-drain output pulled low on current limit, UVLO, or thermal fault; distinct from ALERT for prioritized handling. |
| SDA/SCL (3–4) | I²C data/clock | Bidirectional serial interface pins; require external 2.2–10 kΩ pull-ups to VCC for VR11.1-compliant communication. |
| EN (5) | Enable control input | Logic-high enables PWM outputs and PWRGD; pulling low disables regulation and forces PWRGD low. |
| VSENSE1/ADD (7) | Analog monitor / I²C address | Reconfigures post-startup from 8-address I²C selector to secondary analog voltage monitor (0–2.0 V range). |
| PWM1–PWM6 (31–36) | Phase logic outputs | CMOS-level PWM signals driving external gate drivers (e.g., ADP3121); phase count set by strapping unused PWMx to VCC. |
| SW1–SW6 (25–30) | Current balance inputs | Per-phase switch-node inputs for current-sense amplifier; unused SWx pins must be left floating. |
| VID0–VID7 (38–45) | VR11.1 voltage ID inputs | 8-bit parallel interface defining nominal output voltage; pulled low by CPU; static or on-the-fly reprogrammable. |
| PSI (46) | Power state indicator | Input signaling CPU low-power state; triggers automatic phase shedding and reduced switching frequency. |
| PWRGD (47) | Power-good output | Open-drain signal asserting high when output is within ±5% of programmed VID voltage after soft-start and masking delays. |
| VCC3 (48) | Internal 3.3 V LDO output | On-chip regulated supply for internal logic; requires 1 µF X7R ceramic decoupling capacitor to GND. |
Key Features
| Feature | Design Value |
|---|---|
| VR11.1 Compliance | Fully implements Intel VR11 and VR11.1 specifications including VID encoding, load line positioning, and PSI timing. |
| Active Current Balancing | Hardware-based per-phase current matching across all enabled phases; eliminates need for manual trim resistors or firmware calibration. |
| TRDET Transient Detection | Dedicated output signaling rapid load release events; enables immediate PWM duty-cycle adjustment to minimize undershoot. |
| Programmable Load Line | Configurable droop slope (−350 mV to 0 mV) via I²C; maintains stable voltage positioning under dynamic CPU load transitions. |
| Integrated Thermal Throttling | TTSENSE/VRHOT interface with NTC thermistor support; provides hardware-level thermal shutdown coordination with CPU PROCHOT. |
Applications
| Server CPU Core Power | Desktop PC VRM |
|---|---|
Use Scenario: High-current, multi-phase power delivery to dual-socket Xeon or EPYC processors in 1U/2U rack servers requiring <200 A total output with strict transient response. IC Role / Device Role / Timing Role: Primary multiphase buck controller managing up to six ADP3121 gate drivers; regulates core voltage with <7 mV sensing error and sub-5 µs load-step recovery. Use Value: Enables VR11.1-compliant dynamic voltage scaling, PSI-driven phase shedding, and real-time current telemetry for BMC-based power management. | Use Scenario: ATX motherboard VRM delivering 120 A to high-end Core i9 or Ryzen 9 CPUs with overclocking headroom and thermal margin. IC Role / Device Role / Timing Role: Synchronous buck controller coordinating six external MOSFET drivers; implements programmable soft-start, load-line droop, and crowbar protection per Intel spec. Use Value: Supports on-the-fly VID changes during overclocking, accurate current reporting for BIOS power limiting, and VRHOT-triggered thermal throttling. |
| POL for Memory Subsystem | High-Density Computing Module |
Use Scenario: Point-of-load regulator supplying DDR5 memory VDDQ rails in AI accelerator cards where space-constrained layout demands minimal external components. IC Role / Device Role / Timing Role: Configurable 2- or 3-phase controller using differential sensing (FB/FBRTN) and DCR current sensing; interfaces with memory controller's VID and PSI signals. Use Value: Achieves ±7 mV regulation accuracy at memory die, supports fast load transients via TRDET, and reduces BOM count with integrated 3.3 V LDO (VCC3). | Use Scenario: Compact compute module (e.g., COM-HPC) requiring scalable CPU power with lifecycle continuity and industrial temperature support (0°C to 85°C). IC Role / Device Role / Timing Role: Robust multiphase controller with Pb-free LFCSP-48 package, MSL3 rating, and 260°C reflow compatibility; manages thermal and electrical margins in convection-cooled enclosures. Use Value: Delivers verified VR11.1 compliance, traceable sourcing, and long-term availability for embedded OEM programs with 10+ year design-in horizons. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiphase buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6367IRZ-T | 6-phase VR11.1 controller with SMBus interface; lacks TRDET pin and integrated 3.3 V LDO (VCC3); uses different current-sense topology (IMON only). | Requires external 3.3 V supply and separate transient detection circuitry; less integrated for compact designs. | Choose ISL6367IRZ-T if SMBus-only interface suffices and board space permits discrete 3.3 V regulation. |
| TPS53689TPT | 6-phase PMBus-compatible controller with integrated MOSFET drivers; no dedicated TRDET output; supports higher max output voltage (2.0 V). | Eliminates need for external gate drivers but increases thermal density; lacks VRHOT/TTSENSE direct thermistor interface. | Choose TPS53689TPT for driver-integrated simplicity where thermistor-based thermal monitoring is not required. |
Compared with ISL6367IRZ-T and TPS53689TPT, the ADP4000JCPZ-REEL uniquely combines TRDET-based transient optimization, on-die 3.3 V LDO (VCC3), and dedicated VRHOT/TTSENSE thermal signaling-making it optimal for space-constrained, thermally managed server and high-end desktop VRMs requiring full VR11.1 feature parity.
Availability
ADP4000JCPZ-REEL is available at Aetrix Electronics and suitable for server CPU core power, desktop PC VRM, and POL memory subsystems requiring stable component supply, long-term lifecycle support, and Pb-free RoHS compliance.
Supply support for ADP4000JCPZ-REEL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi is a global semiconductor supplier delivering energy-efficient, intelligent power and sensing solutions for automotive, industrial, cloud, medical, and IoT applications.
The ADP4000 belongs to onsemi's high-performance power management IC portfolio, designed specifically for Intel VR11/VR11.1-compliant multiphase CPU core voltage regulation in servers and high-end computing platforms.
FAQ
What is the primary function of the ADP4000JCPZ-REEL in a CPU power delivery system?
The ADP4000JCPZ-REEL serves as a programmable 6-phase synchronous buck controller that regulates CPU core voltage per Intel VR11.1 specifications. It generates logic-level PWM signals for external gate drivers, implements differential remote sensing (FB/FBRTN), manages current balancing across phases, and supports PSI-driven phase shedding-all coordinated via its I²C interface. The ADP4000JCPZ-REEL enables precise, adaptive voltage positioning under dynamic CPU loads while providing real-time telemetry and fault reporting.
How does the ADP4000JCPZ-REEL achieve ±7 mV differential sensing accuracy?
The ADP4000JCPZ-REEL achieves ±7 mV differential sensing accuracy through a combination of a low-offset error amplifier (typical VOS < 1 mV), precision internal reference (1.8 V ±25 mV), and dedicated FB/FBRTN inputs referenced to the CPU's remote sense point. Its architecture minimizes PCB trace impedance effects by routing FB to the CPU sense pin and FBRTN directly to the CPU ground sense point, while the internal VID DAC and reference are tied to FBRTN. This design maintains worst-case error within ±7 mV across 0–85°C ambient and full output voltage range. The ADP4000JCPZ-REEL's sensing path is validated in Figure 4 of its datasheet.
Can the ADP4000JCPZ-REEL operate with fewer than six phases, and how is phase count configured?
Yes, the ADP4000JCPZ-REEL supports selectable 1-, 2-, 3-, 4-, 5-, or 6-phase operation. Phase count is configured by strapping unused PWMx pins (PWM2–PWM6) to VCC: tying PWM6 to VCC configures 5-phase operation; PWM5+PWM6 to VCC sets 4-phase; and so on down to single-phase (PWM2–PWM6 tied to VCC). During startup, an internal comparator detects these strappings via 100 µA current sinks on PWMx pins. The ADP4000JCPZ-REEL automatically disables unused phases and adjusts clock division (e.g., fSW = fOSC/6 for 6-phase, fOSC/4 for 4-phase) without firmware intervention.
What role does the TRDET pin play in transient response, and how is it used?
The TRDET pin on the ADP4000JCPZ-REEL is a dedicated transient detect output that asserts low whenever a rapid load release (e.g., CPU idle transition) is detected. This signal enables immediate, hardware-accelerated adjustment of PWM duty cycle to suppress output voltage overshoot-bypassing slower I²C or digital loop responses. In typical designs, TRDET connects to an external circuit (e.g., comparator or FPGA input) that triggers auxiliary compensation or disables specific phases. The ADP4000JCPZ-REEL's TRDET functionality is integral to its Fast-Enhanced PWM FlexMode and is documented in Figures 1 and 12 of the datasheet.
Does the ADP4000JCPZ-REEL include integrated power regulation for its own bias supplies?
Yes, the ADP4000JCPZ-REEL integrates two internal regulators: a shunt regulator maintaining VCC at 5.0 V (±5%) from a 12 V system input via a 340 Ω resistor, and a 3.3 V LDO output on pin VCC3 (48) rated for 1 mA with ±100 mV tolerance. The VCC3 supply powers internal logic and requires only a 1 µF X7R ceramic capacitor to ground. This integration eliminates external regulators for bias rails, reducing BOM count and PCB area-critical for dense VRM layouts. The ADP4000JCPZ-REEL's VCC and VCC3 specifications are detailed in Electrical Characteristics Tables on pages 6–9.
ADP4000JCPZ-REEL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Converter, Intel VR11, VR11.1
- Voltage - Input:
- 4.7V ~ 5.75V
- Number of Outputs:
- 6
- Voltage - Output:
- 0.38V ~ 1.8V
- Operating Temperature:
- 0°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-LFCSP (7x7)
ADP4000JCPZ-REEL FAQ
1.How can I place an order for ADP4000JCPZ-REEL through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP4000JCPZ-REEL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP4000JCPZ-REEL reliable?
The price and inventory of ADP4000JCPZ-REEL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP4000JCPZ-REEL is usually 5 days.
3.What payment methods are accepted for ADP4000JCPZ-REEL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP4000JCPZ-REEL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP4000JCPZ-REEL?
ADP4000JCPZ-REEL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP4000JCPZ-REEL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP4000JCPZ-REEL?
For technical support, including ADP4000JCPZ-REEL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP4000JCPZ-REEL requirements.
6.How does Aetrix verify that ADP4000JCPZ-REEL is sourced from the original manufacturer or authorized distributors?
All ADP4000JCPZ-REEL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP4000JCPZ-REEL meets industry standards.
7.What is the process for return or replacement of ADP4000JCPZ-REEL?
All ADP4000JCPZ-REEL units undergo pre-shipment inspection (PSI). If there is an issue with ADP4000JCPZ-REEL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP4000JCPZ-REEL part is unused and in its original packaging.
Return procedure for ADP4000JCPZ-REEL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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