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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - DC DC Switching Regulators

Analog Devices Inc. ADP5014ACPZ-R7

Name: ADP5014ACPZ-R7
Brand: Analog Devices Inc.
SKU: ADP5014ACPZ-R7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADP5014ACPZ-R7

Manufacturer:: Analog Devices Inc.

Category:: Voltage Regulators - DC DC Switching Regulators

Package:: 40-WFQFN Exposed Pad, CSP

Datasheet:: ADP5014ACPZ-R7.pdf

Description:: IC REG BUCK PROG QUAD 40LFCSP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

ADP5014ACPZ-R7 from Analog Devices is a quad-channel, low-noise synchronous buck regulator IC integrating two 4 A-capable channels (Ch1/Ch2) and two 2 A-capable channels (Ch3/Ch4) in a single 40-lead 6 mm × 6 mm LFCSP package. It delivers ±1.0% output voltage accuracy over −40°C to +125°C, supports 500 kHz–2.5 MHz adjustable switching frequency, and achieves ~25 μV_rms output noise at V_OUT ≤ V_REF, enabling clean power for RF transceivers and high-speed ADC/DAC signal chains.

For engineers reviewing the ADP5014ACPZ-R7 datasheet, ADP5014ACPZ-R7 pinout, ADP5014ACPZ-R7 application, or ADP5014ACPZ-R7 equivalent, this device offers programmable parallel operation (up to 8 A from Ch1+Ch2), precision enable with 0.6 V threshold, factory-configurable power-good flags, active output discharge, and comprehensive protection including UVLO, OVP, OCP, and thermal shutdown - critical for FPGA, mixed-signal ASIC, and medical power sequencing.

Technical Context

The ADP5014ACPZ-R7 implements four independent current-mode synchronous buck regulators with integrated high-side and low-side MOSFETs: Ch1/Ch2 feature R_DS(ON) of 49 mΩ/37 mΩ (high/low), supporting 4 A per channel or 8 A in parallel; Ch3/Ch4 use 95 mΩ/73 mΩ MOSFETs for 2 A per channel or 4 A combined. Each channel includes dedicated COMP, FB, VSET, and EN pins, plus shared configuration pins (CFG1/CFG2) for current limit, mode selection, and GPIO mapping.

It supports dual operational modes: manual enable (four individual EN pins) or sequence mode (grouped ENALL with programmable delay timers up to 48 ms per rail), and selectable FPWM/PSM operation. The internal 2.0 V reference exhibits ±0.5% accuracy over temperature, and the RT pin enables precise oscillator programming with external resistor.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	2.75 V to 6.0 V - supports single-cell Li-ion, USB PD, and intermediate bus rails without pre-regulation.
Output Current Capability	Ch1/Ch2: 4 A each or 8 A parallel; Ch3/Ch4: 2 A each or 4 A parallel - enables scalable multi-rail FPGA core/I/O power delivery.
Output Noise	~25 μV_rms at V_OUT ≤ V_REF - meets stringent noise requirements for RF and high-resolution data converters.
Output Accuracy	±1.0% over −40°C to +125°C - ensures stable voltage margins across automotive and industrial operating ranges.
Switching Frequency	500 kHz to 2.5 MHz - allows optimization of size (higher f_SW) vs. efficiency (lower f_SW) with standard 0.8–2.2 µH inductors.
Package	40-lead, 6 mm × 6 mm LFCSP with exposed thermal pad - provides low θ_JA = 40°C/W for high-power density thermal management.
Protection Features	UVLO, OVP, OCP (hiccup mode), TSD, active output discharge - eliminates need for external fault-handling circuitry in safety-critical systems.

Pinout & Package

ADP5014ACPZ-R7 uses a 40-lead, 6 mm × 6 mm LFCSP package with exposed thermal pad (connected to AGND). Pin functions are defined per Analog Devices Rev. A datasheet Figure 3 and Table 5.

Pin/Terminal	Circuit Role	Design Meaning
FB1–FB4	Feedback sensing input per channel	Connects to resistor divider to set output voltage; bias current ≤ 0.1 µA minimizes divider error.
COMP1–COMP4	Error amplifier output per channel	Drives external RC compensation network to stabilize loop response and optimize transient performance.
PVIN1–PVIN4	Power input per channel	Independent inputs allow separate input filtering and source isolation for noise-sensitive rails.
SW1–SW4	Switching node output per channel	Connects to external inductor; requires low-inductance layout to minimize EMI and switching losses.
PGND1–PGND4	Power ground per channel	Dedicated ground returns reduce cross-talk between high-current paths and improve PSRR.
EN1/ENALL–EN4/DL34	Enable/delay control per channel	0.6 V precision threshold enables direct logic-level interfacing; DLx pins program 6–48 ms startup/shutdown delays.
VSET1–VSET4	Reference voltage setting input per channel	Accepts external voltage or resistor divider to configure output as fraction of internal 2.0 V reference.
CFG1, CFG2	System configuration pins	Resistor-programmable settings for current limit, parallel mode, FPWM/PSM, and GPIO function mapping.
RT	Frequency setting input	External resistor to ground sets switching frequency from 500 kHz to 2.5 MHz with ±10% tolerance.
VREF	Internal low-noise reference output	2.0 V ±0.5% output used as precision reference for all channels; drives external dividers or DACs.

Key Features

Feature	Design Value
Quad-channel low-noise buck regulation	Four independent, high-efficiency buck regulators in one package reduce board area by >60% vs. discrete solutions while maintaining <25 μV_rms noise on sensitive rails.
Programmable parallel operation	Ch1+Ch2 combine into single 8 A rail; Ch3+Ch4 combine into single 4 A rail - simplifies high-current design without external current-sharing components.
Configurable power sequencing	Manual or sequence mode with per-rail delay timers (6–48 ms) enables compliance with FPGA, ASIC, and processor boot requirements without external sequencers.
Active output discharge	Integrated discharge switch pulls V_OUT to ground during shutdown - prevents floating outputs and ensures safe state transitions in multi-rail systems.
Factory-programmable power-good	Power-good flag available on select channels via fuse options - eliminates need for external monitoring ICs and reduces BOM count.
Comprehensive protection suite	UVLO, OVP, cycle-by-cycle OCP with hiccup recovery, thermal shutdown, and short-circuit protection - ensures robust operation under fault conditions without external supervision.

Applications

RF Transceiver Power	FPGA Core & I/O Rails
Use Scenario: Powering LTE/5G transceiver analog front-end (LNA, mixer, synthesizer) requiring ultra-low noise and tight voltage regulation. IC Role / Device Role / Timing Role: Primary low-noise DC-DC converter delivering clean 1.2 V, 1.8 V, and 3.3 V rails with simultaneous regulation and fast load transient response. Use Value: ~25 μV_rms output noise preserves SNR and EVM performance; ±1.0% accuracy maintains modulation fidelity across temperature.	Use Scenario: Supplying multiple voltage domains (core, memory, I/O, auxiliary) for Xilinx Zynq or Intel Agilex FPGAs in embedded vision or edge AI systems. IC Role / Device Role / Timing Role: Integrated quad-buck PMU providing sequenced, independently regulated outputs with programmable soft-start and power-good signaling. Use Value: Parallel operation delivers 8 A core rail; per-rail delay timers ensure correct boot order; active discharge prevents latch-up during reconfiguration.
Mixed-Signal ASIC Power	Medical Imaging Signal Chain
Use Scenario: Powering high-speed mixed-signal ASICs in test equipment or optical networking, where digital noise must not couple into analog sections. IC Role / Device Role / Timing Role: Isolated buck regulator per domain (digital core, analog supply, PLL, interface) with dedicated PGNDs and low PSRR design. Use Value: Independent PVIN and PGND pins minimize inter-rail coupling; low-noise architecture prevents spurious tones in ADC/DAC conversion.	Use Scenario: Providing stable, low-noise bias for ultrasound receive beamformers, CT detector front-ends, or MRI gradient amplifiers requiring clinical-grade reliability. IC Role / Device Role / Timing Role: Medical-grade power solution meeting IEC 60601-1 creepage/clearance requirements via compact LFCSP layout and robust thermal design. Use Value: −40°C to +125°C operation supports fanless enclosures; OVP/OCP/TSD protections satisfy safety-critical fault response mandates.

RF Transceiver Power

FPGA Core & I/O Rails

Use Scenario: Powering LTE/5G transceiver analog front-end (LNA, mixer, synthesizer) requiring ultra-low noise and tight voltage regulation.

IC Role / Device Role / Timing Role: Primary low-noise DC-DC converter delivering clean 1.2 V, 1.8 V, and 3.3 V rails with simultaneous regulation and fast load transient response.

Use Value: ~25 μV_rms output noise preserves SNR and EVM performance; ±1.0% accuracy maintains modulation fidelity across temperature.

Use Scenario: Supplying multiple voltage domains (core, memory, I/O, auxiliary) for Xilinx Zynq or Intel Agilex FPGAs in embedded vision or edge AI systems.

IC Role / Device Role / Timing Role: Integrated quad-buck PMU providing sequenced, independently regulated outputs with programmable soft-start and power-good signaling.

Use Value: Parallel operation delivers 8 A core rail; per-rail delay timers ensure correct boot order; active discharge prevents latch-up during reconfiguration.

Mixed-Signal ASIC Power

Medical Imaging Signal Chain

Use Scenario: Powering high-speed mixed-signal ASICs in test equipment or optical networking, where digital noise must not couple into analog sections.

IC Role / Device Role / Timing Role: Isolated buck regulator per domain (digital core, analog supply, PLL, interface) with dedicated PGNDs and low PSRR design.

Use Value: Independent PVIN and PGND pins minimize inter-rail coupling; low-noise architecture prevents spurious tones in ADC/DAC conversion.

Use Scenario: Providing stable, low-noise bias for ultrasound receive beamformers, CT detector front-ends, or MRI gradient amplifiers requiring clinical-grade reliability.

IC Role / Device Role / Timing Role: Medical-grade power solution meeting IEC 60601-1 creepage/clearance requirements via compact LFCSP layout and robust thermal design.

Use Value: −40°C to +125°C operation supports fanless enclosures; OVP/OCP/TSD protections satisfy safety-critical fault response mandates.

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-buck regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS650860RSLR	4-channel buck (3×3 A + 1×2 A); fixed 2.2 MHz f_SW; no VSET pins; integrated LDOs; smaller 7 mm × 7 mm QFN	Targets lower-cost consumer SoC power; lacks low-noise optimization and programmable V_OUT range below 0.5 V	Choose for cost-sensitive, space-constrained SoC designs where noise <50 μV_rms is acceptable and fixed-frequency operation suffices.
MAX20430ATPA/VY+	Quad buck (2×4 A + 2×2 A); 2.2 MHz fixed f_SW; 10-bit I²C interface; no manual enable pins; higher quiescent current (12 mA)	Designed for closed-loop telemetry and remote configuration; requires microcontroller host; no standalone sequencing capability	Choose when dynamic voltage scaling, telemetry, or firmware-controlled sequencing is required - not for pin-strapped or MCU-less systems.

Compared with TPS650860RSLR and MAX20430ATPA/VY+, the ADP5014ACPZ-R7 uniquely combines ultra-low noise (<25 μV_rms), wide programmable f_SW (500 kHz–2.5 MHz), analog VSET inputs for precision voltage setting, and true standalone sequencing - making it optimal for high-performance, noise-sensitive, and safety-critical applications where flexibility and signal integrity are paramount.

Availability

ADP5014ACPZ-R7 is available at Aetrix Electronics and suitable for RF transceiver, FPGA, mixed-signal ASIC, and medical imaging applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for ADP5014ACPZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and a legacy of innovation in precision power, RF, and data conversion.

The ADP5014ACPZ-R7 belongs to Analog Devices' Power Management Unit (PMU) product line, engineered specifically for high-density, low-noise, multi-rail power delivery in signal-chain-intensive systems such as communications infrastructure, test equipment, and advanced medical diagnostics.

FAQ

What is the maximum output current capability of ADP5014ACPZ-R7 per channel?

ADP5014ACPZ-R7 supports up to 4 A per channel on Channels 1 and 2, and up to 2 A per channel on Channels 3 and 4. When configured in parallel, Ch1+Ch2 deliver up to 8 A total, and Ch3+Ch4 deliver up to 4 A total - confirmed in the Buck Regulator Specifications table (Page 5) of the Rev. A datasheet under I_LOAD1, I_LOAD2, I_LOAD3, and I_LOAD4.

Does ADP5014ACPZ-R7 support power sequencing, and how is it implemented?

Yes, ADP5014ACPZ-R7 supports both manual and sequence enable modes. In sequence mode, EN1/ENALL acts as a master enable, while EN2/DL12 and EN4/DL34 serve as delay timer inputs (6–48 ms range) to control startup/shutdown timing for Ch1–Ch2 and Ch3–Ch4 groups respectively - detailed in the General Description and Theory of Operation sections (Pages 1 and 16).

What is the output voltage noise specification for ADP5014ACPZ-R7, and under what conditions is it measured?

ADP5014ACPZ-R7 achieves ~25 μV_rms output noise when V_OUT ≤ V_REF (i.e., ≤2.0 V), as stated in the FEATURES section (Page 1) and GENERAL DESCRIPTION (Page 1). This low-noise performance is enabled by its optimized low-noise architecture and applies across the full load and temperature range under FPWM operation.

Can ADP5014ACPZ-R7 operate with an external clock synchronization signal?

Yes, ADP5014ACPZ-R7 supports frequency synchronization via its SYNC input pin (GPIO pin configurable as CLK-IN), accepting external clocks from 500 kHz to 2.5 MHz with minimum pulse widths of 100 ns - specified in Table 1 (Oscillator Circuit) on Page 4 of the Rev. A datasheet.

What package type and thermal characteristics does ADP5014ACPZ-R7 use?

ADP5014ACPZ-R7 uses a 40-lead, 6 mm × 6 mm LFCSP package with exposed thermal pad. Its thermal resistance is θ_JA = 40°C/W and θ_JC = 11.1°C/W (Table 4, Page 7), enabling efficient heat dissipation in high-power-density layouts when the exposed pad is soldered to a solid ground plane.

ADP5014ACPZ-R7 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 40-WFQFN Exposed Pad, CSP

Packaging:: Tape & Reel (TR)

Product Status:: Active

Function:: Step-Down

Output Configuration:: Positive

Topology:: Buck

Output Type:: Programmable

Number of Outputs:: 4

Voltage - Input (Min):: 2.75V

Voltage - Input (Max):: 6V

Voltage - Output (Min/Fixed):: 0.5V

Voltage - Output (Max):: 4.5V

Current - Output:: 2A, 4A, 1A, 2A

Frequency - Switching:: 500kHz ~ 2.5MHz

Synchronous Rectifier:: No

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 40-LFCSP-WQ (6x6)

ADP5014ACPZ-R7 FAQ

1.How can I place an order for ADP5014ACPZ-R7 through Aetrix?

Please submit a Request for Quotation (RFQ) for ADP5014ACPZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADP5014ACPZ-R7 reliable?

The price and inventory of ADP5014ACPZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5014ACPZ-R7 is usually 5 days.

3.What payment methods are accepted for ADP5014ACPZ-R7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5014ACPZ-R7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADP5014ACPZ-R7?

ADP5014ACPZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADP5014ACPZ-R7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADP5014ACPZ-R7?

For technical support, including ADP5014ACPZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5014ACPZ-R7 requirements.

6.How does Aetrix verify that ADP5014ACPZ-R7 is sourced from the original manufacturer or authorized distributors?

All ADP5014ACPZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5014ACPZ-R7 meets industry standards.

7.What is the process for return or replacement of ADP5014ACPZ-R7?

All ADP5014ACPZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5014ACPZ-R7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADP5014ACPZ-R7 part is unused and in its original packaging.

Return procedure for ADP5014ACPZ-R7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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