Analog Devices Inc. ADP5022ACBZ-6-R7

Overview

ADP5022ACBZ-6-R7 from Analog Devices is a dual-buck + single-LDO power management IC integrating two 800 mA, 3 MHz synchronous step-down regulators and one 300 mA low-noise LDO in a 24-lead 4 mm × 4 mm LFCSP package. It delivers tightly regulated 0.8–3.8 V buck outputs and 0.8–5.2 V LDO output with ±1.8% accuracy, high PSRR (>60 dB at 10 kHz), and out-of-phase buck operation for reduced input ripple - ideal for FPGA core/IO rail sequencing in space-constrained portable instrumentation.

For engineers reviewing the ADP5022ACBZ-6-R7 datasheet, ADP5022ACBZ-6-R7 pinout, ADP5022ACBZ-6-R7 application, or ADP5022ACBZ-6-R7 equivalent, key selection criteria include its factory-programmed output voltages (VOUT1 = 1.2 V, VOUT2 = 1.8 V, VOUT3 = 3.3 V), forced PWM/auto PSM mode control via MODE pin, 2.3–5.5 V main input range, and thermal shutdown at 150°C with 20°C hysteresis.

Technical Context

The ADP5022ACBZ-6-R7 implements independent enable-controlled regulation: EN1/EN2 activate BUCK1/BUCK2 (800 mA each), while EN3 controls the 300 mA LDO. Its MODE pin selects between fixed 3 MHz forced PWM operation (high) or auto PWM/PSM mode (low), where light-load efficiency improves via pulse-skipping below 100 mA threshold. The buck regulators operate 180° out of phase to minimize input capacitor RMS current.

Internally, the device uses separate analog ground (AGND) and power ground (PGND1/PGND2) planes, dedicated feedback pins (FB1/FB2/FB3) supporting both fixed and adjustable configurations, and integrated soft-start (250–300 µs startup time). The LDO features low dropout (75 mV at 3.3 V/300 mA), 100 µV_rms output noise (10 Hz–100 kHz), and maintains >60 dB PSRR up to 1 MHz.

Key Specifications

Pinout & Package

ADP5022ACBZ-6-R7 is housed in a 24-lead, 4 mm × 4 mm, 0.5 mm pitch LFCSP package with exposed thermal pad (EPAD) recommended for soldering to PCB ground plane. Pin 6 is NC (no connect); all AGND pins (1, 2, 18, 23, 24) must be tied to analog ground; PGND1 (14) and PGND2 (5) are dedicated power grounds for BUCK1 and BUCK2 respectively.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail power management applications.

Compared with ADP5023ACBZ-6-R7, the ADP5022ACBZ-6-R7 shares identical silicon and performance but may reflect a specific tape-and-reel packaging variant; versus TPS65023RGZR, it trades off LDO count and peak current for significantly lower noise, smaller footprint, and simpler layout.

Availability

ADP5022ACBZ-6-R7 is available at Aetrix Electronics and suitable for FPGA power sequencing, portable medical instrumentation, and space-constrained IoT edge nodes requiring stable component supply, guaranteed long-term availability, and full compliance with RoHS and REACH directives.

Supply support for ADP5022ACBZ-6-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP5022ACBZ-6-R7 belongs to the ADP502x micro PMU family, engineered specifically for space-constrained portable and medical electronics requiring high-efficiency, low-noise, and multi-rail power integration in minimal PCB area.

FAQ

What are the factory-programmed output voltages of the ADP5022ACBZ-6-R7?

The ADP5022ACBZ-6-R7 is factory-programmed to deliver VOUT1 = 1.2 V, VOUT2 = 1.8 V, and VOUT3 = 3.3 V. These fixed outputs eliminate the need for external feedback resistors, reduce component count, and ensure ±1.8% accuracy across −40°C to +125°C junction temperature. The ADP5022ACBZ-6-R7 datasheet confirms these values in the Ordering Guide and Typical Application Circuit.

Does the ADP5022ACBZ-6-R7 support independent enable control for each regulator?

Yes, the ADP5022ACBZ-6-R7 provides three dedicated enable pins: EN1 for BUCK1, EN2 for BUCK2, and EN3 for the LDO. Each is active-high and electrically isolated, allowing precise power sequencing - for example, enabling the 3.3 V LDO before the 1.2 V buck to meet FPGA I/O initialization requirements. This capability is explicitly defined in the Pin Function Descriptions section of the ADP5022ACBZ-6-R7 datasheet.

What is the maximum allowable input voltage for the LDO section of the ADP5022ACBZ-6-R7?

The LDO input (VIN3) of the ADP5022ACBZ-6-R7 accepts 1.7 V to 5.5 V. Absolute maximum rating is AVIN + 0.3 V, with AVIN rated up to 6 V. For reliable operation, VIN3 must exceed VOUT3 by at least 0.5 V (e.g., 3.8 V min for 3.3 V output). This specification is confirmed in Table 4 (LDO Specifications) and Absolute Maximum Ratings (Table 6) of the ADP5022ACBZ-6-R7 datasheet.

How does the MODE pin affect the buck regulators in the ADP5022ACBZ-6-R7?

When MODE is high, both buck regulators operate in forced PWM mode at a constant 3 MHz switching frequency regardless of load. When MODE is low, they switch to auto PWM/PSM mode - maintaining fixed frequency above 100 mA load and entering power-save mode below that threshold to improve light-load efficiency. This behavior is detailed in the General Description and Theory of Operation sections of the ADP5022ACBZ-6-R7 datasheet.

Is the ADP5022ACBZ-6-R7 pin-compatible with other members of the ADP502x family?

Yes, the ADP5022ACBZ-6-R7 shares identical 24-lead LFCSP (CP-24-10) packaging and pinout with ADP5023ACBZ-6-R7 and ADP5037ACBZ-6-R7. All feature matching AGND, PGND, EN, FB, VOUT, SW, VIN, and MODE pin assignments. This compatibility is verified in the Pin Configuration diagrams and Package Outline Dimensions (Page 27) of the ADP5022ACBZ-6-R7 datasheet.