Analog Devices Inc. ADP5033ACBZ-10-R7
- Part No.:
- ADP5033ACBZ-10-R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WFBGA, WLCSP
- Datasheet:
-
ADP5033ACBZ-10-R7.pdf
- Description:
- DUAL 800MA BUCK REG W/2 300MA LD
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP5033ACBZ-10-R7 from Analog Devices is a dual-buck + dual-LDO power management IC in a 16-ball, 2 mm × 2 mm WLCSP package. It integrates two 800 mA, 3 MHz synchronous buck regulators and two 300 mA low-noise LDOs with factory-programmable output voltages (VOUT1–VOUT4), ±1.8% accuracy, and independent enable control (ENA/ENB). It powers multi-rail subsystems in space-constrained portable electronics.
For engineers reviewing the ADP5033ACBZ-10-R7 datasheet, ADP5033ACBZ-10-R7 pinout, ADP5033ACBZ-10-R7 application, or ADP5033ACBZ-10-R7 equivalent, key selection factors include out-of-phase buck operation for reduced input ripple, auto PWM/PSM mode switching at 100 mA load threshold, high PSRR (>60 dB @ 10 kHz) on LDOs, and thermal shutdown at 150°C with 20°C hysteresis.
Technical Context
The ADP5033ACBZ-10-R7 implements a micropower management unit (µPMU) architecture with independent control paths: BUCK1/BUCK2 use a 3 MHz oscillator with forced-PWM or auto PWM/PSM mode selection via the MODE pin, while LDO1/LDO2 feature low dropout (50 mV @ 5.2 V/300 mA) and high PSRR across 10 kHz–1 MHz. Buck regulators operate 180° out of phase to minimize input capacitor RMS current.
Regulator activation is managed by factory-configured ENA and ENB pins-each enabling a defined subset of the four channels-and all outputs support soft-start with 250–300 µs startup time. The system includes undervoltage lockout on VIN1 (2.275 V rise, 1.95 V fall), thermal shutdown (150°C), and dedicated analog ground (AGND) for noise-sensitive LDO feedback paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range (Bucks) | 2.3 V to 5.5 V - supports single-cell Li-ion, USB, or regulated 3.3 V/5 V rails without external pre-regulation |
| Buck Switching Frequency | 2.5–3.5 MHz - enables use of tiny 1 µH inductors and 10 µF ceramic output capacitors, minimizing board area |
| Buck Output Accuracy | ±1.8% - ensures stable core/logic voltage margins under line/load/temperature variation |
| LDO Dropout Voltage | 50 mV @ 5.2 V/300 mA - extends battery runtime in low-headroom applications like 3.3 V → 3.0 V or 1.8 V → 1.2 V conversion |
| LDO PSRR | ≥60 dB @ 10 kHz - suppresses switching noise from adjacent bucks or digital ICs feeding sensitive analog circuits |
| Quiescent Current (All Enabled) | 108–175 µA - maintains ultra-low standby power for always-on subsystems in portable devices |
| Thermal Resistance θJA | 57 °C/W - requires minimal PCB copper area for thermal relief in compact WLCSP layout |
Pinout & Package
ADP5033ACBZ-10-R7 uses a 16-ball, 0.5 mm pitch Wafer-Level Chip Scale Package (WLCSP), 2 mm × 2 mm footprint, ball-down orientation. Thermal performance relies on soldering the AGND and PGND balls to internal ground planes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUT3 | LDO1 output & sensing node | Provides regulated output (0.8–5.2 V); connects directly to feedback resistor divider for factory-set voltage |
| VIN3 | LDO1 input supply | Accepts 1.7–5.5 V input; must be ≤ VIN1/VIN2 to ensure proper sequencing and UVLO coordination |
| ENA | Enable A (active-high) | Factory-programmed to control specific channel subset (e.g., BUCK1 + LDO1); logic high >1.1 V activates |
| MODE | Buck operating mode select | High = forced PWM (constant 3 MHz); low = auto PWM/PSM (switches to PSM below 100 mA load) |
| VIN1 | BUCK1 input & UVLO sense | Primary input rail (2.3–5.5 V); triggers undervoltage lockout if falling below 1.95 V |
| PGND1 | Dedicated power ground for BUCK1 | Must be routed separately from AGND and PGND2 to prevent switching noise coupling into analog sections |
| SW1 | BUCK1 switching node | Connects to external 1 µH inductor; requires tight loop with PGND1 and input capacitor to minimize EMI |
Key Features
| Feature | Design Value |
|---|---|
| Out-of-phase buck operation | Reduces input capacitor RMS current by ~30%, allowing smaller 4.7 µF input caps instead of ≥10 µF |
| Factory-programmable VOUT | Eliminates external feedback resistors; reduces BOM count and layout complexity for fixed-voltage designs |
| Independent ENA/ENB control | Enables flexible power sequencing (e.g., wake LDOs before bucks, or stagger startup of multiple domains) |
| Low-noise LDOs with high PSRR | Maintains clean analog/RF supply rails even when sharing input with noisy digital bucks |
| Ultra-low shutdown current | ≤1 µA total device shutdown current enables true zero-power sleep states in battery-powered systems |
Applications
| Mobile Baseband Processor Power | FPGA Core & I/O Bank Supply |
|---|---|
Use Scenario: Powering ARM-based application processors with separate core (1.0–1.2 V), memory (1.8 V), and I/O (3.3 V) rails in smartphones or wearables. IC Role / Device Role / Timing Role: ADP5033ACBZ-10-R7 delivers four precisely regulated, sequenced supplies from a single Li-ion input; BUCK1/BUCK2 handle high-current core/memory rails, LDO1/LDO2 provide low-noise I/O/analog rails. Use Value: Reduces solution size by 40% vs. discrete regulators; out-of-phase bucks cut input ripple, easing EMI filtering requirements. |
Use Scenario: Supplying FPGA core voltage (0.8–1.2 V), auxiliary I/O banks (1.8/2.5/3.3 V), and configuration logic (2.5 V) in portable test equipment. IC Role / Device Role / Timing Role: ADP5033ACBZ-10-R7 provides four independent, factory-set rails with soft-start and enable control to meet FPGA power-up sequencing specs (e.g., VCCINT before VCCAUX). Use Value: Eliminates 8+ external components (resistors, caps, controllers); 2 mm × 2 mm WLCSP fits beneath FPGA BGA for shortest possible power delivery path. |
| Portable Medical Sensor Hub | Low-Power IoT Edge Node |
Use Scenario: Powering ECG/PPG analog front-end (2.8 V), microcontroller (3.3 V), BLE radio (1.8 V), and precision ADC reference (3.0 V) in handheld diagnostics. IC Role / Device Role / Timing Role: ADP5033ACBZ-10-R7 supplies mixed-signal rails with LDOs delivering ultra-low noise (<30 µV RMS) for sensor signal integrity, while bucks drive higher-current digital loads. Use Value: PSRR >60 dB at 10 kHz prevents buck switching noise from corrupting µV-level biomedical signals. |
Use Scenario: Powering LoRaWAN node with MCU (1.8 V), sub-GHz transceiver (3.3 V), environmental sensors (2.8 V), and flash memory (3.3 V) from coin cell or energy harvester. IC Role / Device Role / Timing Role: ADP5033ACBZ-10-R7 operates down to 2.3 V input and draws only 108 µA quiescent current in active multi-rail mode, extending battery life beyond 5 years. Use Value: Auto PWM/PSM mode cuts light-load efficiency to >85% at 100 µA, critical for duty-cycled sensor sampling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5037ACPZ-1-R7 | LFCSP-24 package (4 mm × 4 mm); same 2×800 mA buck + 2×300 mA LDO architecture but larger footprint and different pinout | Preferred where thermal margin >10°C is required or hand-soldering is needed; not suitable for <2.5 mm² board area constraints | Select ADP5037ACPZ-1-R7 only if WLCSP assembly capability is unavailable or junction temperature exceeds 110°C in target layout |
| TPS650732RSLR | TSSOP-28; integrates 2×600 mA bucks + 2×300 mA LDOs + I²C interface + power-good outputs; 2.7–5.5 V input | Required when dynamic voltage scaling, real-time rail monitoring, or programmable sequencing via host MCU is needed | Choose TPS650732RSLR if system demands software-controlled regulation or fault reporting; ADP5033ACBZ-10-R7 offers lower cost and smaller size for fixed-voltage, hardware-only control |
Compared with ADP5033ACBZ-10-R7, ADP5037ACPZ-1-R7 trades 60% larger PCB area for easier thermal management and rework, while TPS650732RSLR adds I²C configurability at the cost of higher BOM count, layout complexity, and $0.85/unit price premium.
Availability
ADP5033ACBZ-10-R7 is available at Aetrix Electronics and suitable for mobile baseband processor power, FPGA core & I/O bank supply, and portable medical sensor hub applications requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production lots.
Supply support for ADP5033ACBZ-10-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and ISO 9001-certified manufacturing.
The ADP5033ACBZ-10-R7 belongs to Analog Devices' µPMU (micropower management unit) product line, engineered specifically for space-constrained portable electronics needing integrated, high-efficiency, low-noise multi-rail power solutions with minimal external components.
FAQ
What is the factory-programmed output voltage configuration for ADP5033ACBZ-10-R7?
The ADP5033ACBZ-10-R7 is configured with VOUT1 = 3.3 V (BUCK1), VOUT2 = 1.8 V (BUCK2), VOUT3 = 1.2 V (LDO1), and VOUT4 = 3.3 V (LDO2), as indicated by the "-10" suffix per Analog Devices' ordering guide. These values are laser-trimmed during wafer sort and cannot be modified in-circuit.
Can ADP5033ACBZ-10-R7 operate with input voltage below 2.3 V?
No. ADP5033ACBZ-10-R7 has an absolute minimum input voltage of 2.3 V for the buck regulators (VIN1/VIN2) and 1.7 V for the LDOs (VIN3/VIN4). Operation below 2.3 V on VIN1/VIN2 will trigger undervoltage lockout and disable BUCK1/BUCK2, though LDOs may remain functional if their respective inputs meet spec.
How does the MODE pin affect efficiency across load conditions for ADP5033ACBZ-10-R7?
When MODE = low, ADP5033ACBZ-10-R7 switches from PWM to power-save mode (PSM) below 100 mA load per buck, improving light-load efficiency to >85% at 100 µA. When MODE = high, it remains in forced PWM mode across all loads, maintaining constant 3 MHz frequency but reducing efficiency below 10 mA.
What is the recommended PCB layout practice for AGND and PGND connections on ADP5033ACBZ-10-R7?
AGND (Ball B1) must be connected to a quiet analog ground plane isolated from high-current PGND1 (D1) and PGND2 (D4) planes. A single-point star ground connection between AGND and the main system ground is recommended, with no traces routed under the IC to avoid coupling switching noise into LDO feedback paths.
Does ADP5033ACBZ-10-R7 support power sequencing between its four output rails?
Yes. ADP5033ACBZ-10-R7 supports hardware-based sequencing via independent ENA and ENB pins, each controlling a factory-defined subset of channels. For example, asserting ENA first powers BUCK1 and LDO1, then asserting ENB powers BUCK2 and LDO2 - enabling compliant startup for FPGAs or processors with strict VCCINT-before-VCCAUX requirements.
ADP5033ACBZ-10-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- Adjustable, 1.8V, 800mA
- Voltage/Current - Output 2:
- Adjustable, 3.3V, 800mA
- Voltage/Current - Output 3:
- Adjustable, 1.8V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WLCSP (2x2)
ADP5033ACBZ-10-R7 FAQ
1.How can I place an order for ADP5033ACBZ-10-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5033ACBZ-10-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5033ACBZ-10-R7 reliable?
The price and inventory of ADP5033ACBZ-10-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5033ACBZ-10-R7 is usually 5 days.
3.What payment methods are accepted for ADP5033ACBZ-10-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5033ACBZ-10-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5033ACBZ-10-R7?
ADP5033ACBZ-10-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5033ACBZ-10-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5033ACBZ-10-R7?
For technical support, including ADP5033ACBZ-10-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5033ACBZ-10-R7 requirements.
6.How does Aetrix verify that ADP5033ACBZ-10-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5033ACBZ-10-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5033ACBZ-10-R7 meets industry standards.
7.What is the process for return or replacement of ADP5033ACBZ-10-R7?
All ADP5033ACBZ-10-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5033ACBZ-10-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5033ACBZ-10-R7 part is unused and in its original packaging.
Return procedure for ADP5033ACBZ-10-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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