My Inquiry
My Account
Analog Devices Inc. ADP5033ACBZ-1-R7
- Part No.:
- ADP5033ACBZ-1-R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WFBGA, WLCSP
- Datasheet:
-
ADP5033ACBZ-1-R7.pdf
- Description:
- IC REG QUAD BCK/LNR SYNC 16WLCSP
- Quantity:
- Payment:
- Shipping:
Inventory:2,203
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADP5033ACBZ-1-R7 from Analog Devices is a dual-buck + dual-LDO power management IC in a 16-ball, 2 mm × 2 mm WLCSP package. It integrates two 800 mA, 3 MHz synchronous buck regulators and two 300 mA low-noise LDOs with ±1.8% output accuracy, factory-programmable VOUT, and out-of-phase buck operation - enabling compact, high-efficiency power for space-constrained portable processors and RF chipsets.
For engineers reviewing the ADP5033ACBZ-1-R7 datasheet, ADP5033ACBZ-1-R7 pinout, ADP5033ACBZ-1-R7 application, or ADP5033ACBZ-1-R7 equivalent, key selection considerations include its dual-buck/LDO integration, forced PWM/auto PSM mode control via MODE pin, 2.3 V–5.5 V main input range, and WLCSP thermal resistance (θJA = 57°C/W) for thermally demanding embedded designs.
Technical Context
The ADP5033ACBZ-1-R7 implements a micropower management unit (µPMU) with independent enable control (ENA/ENB) for regulator grouping, out-of-phase buck switching to reduce input ripple, and dedicated analog ground (AGND) with separate power grounds (PGND1/PGND2). Its buck regulators feature programmable 2.5–3.5 MHz switching frequency, PFET/NFET on-resistance specs (e.g., RPFET = 145–235 mΩ at VIN1 = 5 V), and 100 mA PSM-to-PWM transition threshold.
LDO1 and LDO2 operate from 1.7 V–5.5 V inputs, deliver ≤110 mV dropout at 3.3 V/300 mA, achieve ≥60 dB PSRR up to 1 MHz, and maintain <0.003%/mA load regulation. Factory-programmed VOUTx values are fixed per unit; no runtime voltage adjustment is supported.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Main Input Range | VIN1/VIN2 = 2.3 V to 5.5 V - supports single-cell Li-ion, USB, and wide-input industrial rails |
| Buck Output Current | 800 mA per channel - sufficient for core logic or memory rails in FPGAs and ASICs |
| LDO Output Current | 300 mA per channel - powers analog sensors, RF bias, or low-noise peripherals |
| Switching Frequency | 2.5–3.5 MHz (typ. 3 MHz) - enables use of 1 µH inductors and small ceramic capacitors |
| Output Accuracy | ±1.8% for all four outputs - ensures stable voltage margins under load and temperature variation |
| Thermal Resistance | θJA = 57°C/W - requires minimal PCB copper area for thermal management in WLCSP layout |
| PSRR (LDO) | ≥60 dB at 10 kHz–1 MHz - suppresses switching noise from bucks or upstream sources |
Pinout & Package
ADP5033ACBZ-1-R7 uses a 16-ball, 0.5 mm pitch Wafer-Level Chip Scale Package (WLCSP, CB-16-8), optimized for ultra-compact PCB footprints and thermal performance in portable systems.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUT3 | LDO1 output & feedback node | Provides regulated analog supply; connects directly to LDO1 output capacitor and load |
| VIN3 | LDO1 input supply | Accepts 1.7 V–5.5 V input; must be ≥ VOUT3 + 0.5 V for proper dropout margin |
| VIN4 | LDO2 input supply | Independent 1.7 V–5.5 V input; supports different source than VIN3 for noise isolation |
| VOUT4 | LDO2 output & feedback node | Digital rail output; shares same accuracy and PSRR specs as VOUT3 |
| AGND | Analog reference ground | Must be connected to clean analog ground plane; separates from PGND1/PGND2 to minimize noise coupling |
| MODE | Buck operating mode control | High = forced PWM (constant frequency); Low = auto PWM/PSM (light-load efficiency optimization) |
| ENA / ENB | Grouped regulator enable inputs | Active-high pins; factory-programmed to control specific buck/LDO combinations |
| VIN1 / VIN2 | Buck1/Buck2 input supplies | Connected together per design; UVLO active on VIN1 (2.275 V rise, 1.95 V fall) |
| VOUT1 / VOUT2 | Buck1/Buck2 feedback inputs | Resistive divider connection points; set nominal output voltage (0.8 V–3.8 V) |
| SW1 / SW2 | Buck switching nodes | Connect to external inductor; require low-ESR ceramic caps and careful routing to minimize EMI |
| PGND1 / PGND2 | Dedicated buck power grounds | Separate return paths for each buck stage to prevent ground bounce and cross-talk |
Key Features
| Feature | Design Value |
|---|---|
| Out-of-phase buck operation | Reduces RMS input current ripple by ~30%, allowing smaller input capacitors (min. 4.7 µF) |
| Factory-programmable VOUT | Eliminates external resistor networks; reduces BOM count and layout complexity |
| Low-quiescent-current LDOs | 74 µA total system current with both LDOs enabled and bucks disabled - extends battery life |
| High PSRR LDO architecture | 60–64 dB rejection up to 1 MHz - preserves signal integrity in RF and precision analog circuits |
| Thermal shutdown with hysteresis | 150°C trip with 20°C hysteresis - prevents latch-up and enables safe recovery after overload |
Applications
| Processor Power Supply | FPGA Core & I/O Rails |
|---|---|
Use Scenario: Powering ARM Cortex-A series SoCs with multiple voltage domains (core, memory, I/O). IC Role / Device Role / Timing Role: Provides tightly regulated, low-noise 1.0 V/1.2 V core and 1.8 V/3.3 V I/O supplies from a single 3.6 V Li-ion source. Use Value: Dual buck regulators deliver high efficiency (>90% at 500 mA), while dual LDOs supply clean analog/PLL rails with >60 dB PSRR at 1 MHz. |
Use Scenario: Supporting Xilinx Artix-7 FPGA requiring independent 1.0 V core, 1.8 V transceiver, and 3.3 V configuration rails. IC Role / Device Role / Timing Role: BUCK1 and BUCK2 generate core and transceiver voltages; LDO1/LDO2 provide low-noise configuration and auxiliary supplies. Use Value: Out-of-phase buck switching minimizes input capacitor stress; factory-set VOUT eliminates trimming resistors and saves board area. |
| Portable Medical Sensor Hub | RF Front-End Power |
Use Scenario: Powering ECG/SpO₂ sensor modules with analog front-end, ADC, and BLE radio in wearable form factor. IC Role / Device Role / Timing Role: LDO1 supplies ultra-low-noise 2.8 V to ADC reference; LDO2 powers BLE radio; bucks supply digital logic. Use Value: LDO PSRR ≥60 dB at 10 kHz–1 MHz rejects switching noise, preserving ADC SNR; WLCSP footprint fits sub-10 cm² PCBs. |
Use Scenario: Delivering stable, low-noise bias to GaAs pHEMT amplifiers and mixer ICs in 5G mmWave test equipment. IC Role / Device Role / Timing Role: LDO2 provides 5.0 V/300 mA RF bias; BUCK1 supplies 3.3 V digital control; AGND separation isolates analog paths. Use Value: 50 mV dropout at 5.2 V/300 mA ensures headroom under load; 1.7 V minimum LDO input supports partial battery discharge. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5037ACPZ-2-R7 | LFCSP-24 package (4 mm × 4 mm); higher thermal mass; same 2×800 mA buck + 2×300 mA LDO topology | Better thermal performance (θJA = 42°C/W) but larger footprint; suited for higher ambient or sustained load conditions | Select when board space allows and junction temperature margin is critical above 85°C ambient |
| ADP5133ACBZ-1-R7 | WLCSP-16 package, identical footprint; only two 800 mA bucks - no integrated LDOs | Requires external LDOs for analog/low-noise rails; increases BOM and layout complexity but improves flexibility | Select when LDO requirements are nonstandard (e.g., >300 mA, adjustable VOUT, or ultra-low IQ) |
Compared with ADP5033ACBZ-1-R7, ADP5037 offers superior thermal handling in larger systems, while ADP5133 trades integrated LDOs for buck-only simplicity and external regulator choice - making ADP5033ACBZ-1-R7 optimal for space-constrained, fully integrated dual-domain power where factory-programmed outputs suffice.
Availability
ADP5033ACBZ-1-R7 is available at Aetrix Electronics and suitable for portable instrumentation, medical wearables, and space-constrained RF chipsets requiring stable component supply, long-term lifecycle support, and verified WLCSP assembly compatibility.
Supply support for ADP5033ACBZ-1-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The ADP5033ACBZ-1-R7 belongs to Analog Devices' µPMU (micropower management unit) product line, designed specifically for ultra-compact, high-efficiency power delivery in battery-powered and thermally constrained applications such as portable diagnostics and wireless edge devices.
FAQ
What is the maximum output voltage supported by the buck regulators in ADP5033ACBZ-1-R7?
The buck regulators in ADP5033ACBZ-1-R7 support an output voltage range of 0.8 V to 3.8 V. This range is set by external resistor dividers connected to the VOUT1 and VOUT2 pins, and the value is fixed per unit due to factory programming - no post-manufacture adjustment is possible without modifying the feedback network.
Does ADP5033ACBZ-1-R7 support dynamic voltage scaling (DVS) or real-time output voltage adjustment?
No, ADP5033ACBZ-1-R7 does not support dynamic voltage scaling or real-time output voltage adjustment. Its output voltages are factory-programmed during production and remain fixed. Voltage changes require hardware modification of the external feedback resistors or selection of a different variant from the ADP5033 family.
How is thermal performance managed in the WLCSP package of ADP5033ACBZ-1-R7?
ADP5033ACBZ-1-R7 uses a 16-ball WLCSP with θJA = 57°C/W and ΨJB = 14°C/W. Effective thermal management requires soldering to a well-designed PCB with thermal vias under the package and adequate copper pour on inner layers. The device includes thermal shutdown at 150°C with 20°C hysteresis to prevent damage during transient overloads.
Can the LDOs in ADP5033ACBZ-1-R7 operate independently of the buck regulators?
Yes - the LDOs (LDO1/LDO2) and buck regulators (BUCK1/BUCK2) in ADP5033ACBZ-1-R7 can be enabled or disabled independently via the factory-configured ENA and ENB pins. Each pin controls a preassigned group; for example, ENA may activate BUCK1 and LDO1, while ENB activates BUCK2 and LDO2 - enabling flexible power sequencing.
What is the minimum input voltage required for the LDOs in ADP5033ACBZ-1-R7 to regulate properly?
The LDOs in ADP5033ACBZ-1-R7 require a minimum input voltage of 1.7 V, but actual minimum depends on output voltage and load: VIN ≥ VOUT + dropout voltage. At 300 mA load, dropout is 50–165 mV depending on VOUT (e.g., 65 mV at 3.3 V). Therefore, for a 3.3 V LDO output, VIN must be ≥3.365 V to maintain regulation.
ADP5033ACBZ-1-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 1.2V, 800mA
- Voltage/Current - Output 2:
- 3.3V, 800mA
- Voltage/Current - Output 3:
- 2.8V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WLCSP (2x2)
ADP5033ACBZ-1-R7 FAQ
1.How can I place an order for ADP5033ACBZ-1-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5033ACBZ-1-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5033ACBZ-1-R7 reliable?
The price and inventory of ADP5033ACBZ-1-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5033ACBZ-1-R7 is usually 5 days.
3.What payment methods are accepted for ADP5033ACBZ-1-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5033ACBZ-1-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5033ACBZ-1-R7?
ADP5033ACBZ-1-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5033ACBZ-1-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5033ACBZ-1-R7?
For technical support, including ADP5033ACBZ-1-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5033ACBZ-1-R7 requirements.
6.How does Aetrix verify that ADP5033ACBZ-1-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5033ACBZ-1-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5033ACBZ-1-R7 meets industry standards.
7.What is the process for return or replacement of ADP5033ACBZ-1-R7?
All ADP5033ACBZ-1-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5033ACBZ-1-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5033ACBZ-1-R7 part is unused and in its original packaging.
Return procedure for ADP5033ACBZ-1-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADP5033ACBZ-1-R7 Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
