Analog Devices Inc. ADP5033ACBZ-4-R7

Overview

ADP5033ACBZ-4-R7 from Analog Devices is a dual-buck + dual-LDO power management IC integrating two 800 mA, 3 MHz synchronous step-down regulators and two 300 mA low-dropout linear regulators in a single 2 mm × 2 mm WLCSP package. It delivers precise, low-noise, high-PSRR voltage regulation for mixed-signal SoCs, with factory-programmable output voltages (BUCK1/BUCK2: 0.8–3.8 V; LDO1/LDO2: 0.8–5.2 V) and ±1.8% output accuracy across temperature.

For engineers reviewing the ADP5033ACBZ-4-R7 datasheet, ADP5033ACBZ-4-R7 pinout, ADP5033ACBZ-4-R7 application, or ADP5033ACBZ-4-R7 equivalent, key selection criteria include out-of-phase buck operation to reduce input ripple, auto PWM/PSM mode switching at 100 mA load threshold, 60 dB PSRR at 10 kHz for LDO1, and dedicated analog/digital LDO partitioning for noise-sensitive RF and processor domains.

Technical Context

The ADP5033ACBZ-4-R7 implements a tightly integrated µPMU architecture with independent enable control (ENA/ENB) for regulator grouping, MODE-pin-selectable forced PWM or auto PWM/PSM operation, and out-of-phase buck switching to minimize input capacitor RMS current. Its dual LDOs feature separate input supplies (VIN3/VIN4), low dropout (50 mV @ 5.2 V/300 mA), and high PSRR maintained up to 1 MHz.

Buck regulation uses internal PFET/NFET switches with R_PFET = 145–295 mΩ and R_NFET = 110–220 mΩ (depending on VIN), while LDOs employ low-quiescent-current bias networks (10–245 µA per LDO) and active pull-down (600 Ω) for fast turn-off. Thermal shutdown activates at 150°C with 20°C hysteresis, and junction temperature is rated to +125°C.

Key Specifications

Pinout & Package

ADP5033ACBZ-4-R7 is housed in a 16-ball, 0.5 mm pitch Wafer-Level Chip Scale Package (WLCSP, CB-16-8), optimized for ultra-compact PCB layouts with minimal thermal resistance (θ_JA = 57°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail power management applications.

Compared with ADP5033ACBZ-4-R7, ADP5037ACPZ-4-R7 offers superior thermal performance in larger form factor, while ADP5133ACBZ-4-R7 reduces solution size and cost by omitting integrated LDOs - both require PCB redesign and cannot substitute without validation.

Availability

ADP5033ACBZ-4-R7 is available at Aetrix Electronics and suitable for portable instrumentation, medical wearables, and space-constrained FPGA/ASIC power delivery requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for ADP5033ACBZ-4-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP5033 belongs to Analog Devices' µPMU (micropower management unit) product line, engineered specifically for space- and efficiency-critical applications in portable, medical, and industrial electronics where integration, low noise, and small footprint are essential.

FAQ

What is the factory-programmed output voltage configuration for ADP5033ACBZ-4-R7?

The ADP5033ACBZ-4-R7 is configured with fixed output voltages set at wafer test: BUCK1 = 3.3 V, BUCK2 = 1.8 V, LDO1 = 1.2 V, and LDO2 = 3.3 V. These values are laser-trimmed and non-adjustable in-circuit; no external resistors are required for feedback. The -4 suffix in the part number explicitly denotes this factory setting, confirmed in Analog Devices' Ordering Guide (Rev. H, Page 26).

Does ADP5033ACBZ-4-R7 support independent enable control for each regulator?

No - ADP5033ACBZ-4-R7 uses grouped enable logic. ENA and ENB are factory-programmed to activate specific regulator subsets (e.g., ENA may control BUCK1 + LDO1, ENB controls BUCK2 + LDO2). The exact mapping is fixed per variant and cannot be modified; Table 1 in the datasheet confirms ADP5033 has "2 EN pins" for grouped control, unlike ADP5034/ADP5134 which offer per-channel enable.

Can ADP5033ACBZ-4-R7 operate with input voltage below 2.3 V?

No - the buck regulators (BUCK1/BUCK2) require VIN1/VIN2 ≥ 2.3 V per Absolute Maximum Ratings and General Specifications (Page 3). While LDO inputs accept as low as 1.7 V, the buck stages will not start or regulate below 2.3 V. UVLO activation occurs at 2.275 V (rising) and 1.95 V (falling), so operation below 2.3 V risks unregulated or disabled behavior.

What is the maximum supported output capacitance for ADP5033ACBZ-4-R7's LDOs?

The datasheet specifies a minimum output capacitance of 1.0 µF for LDO1/LDO2 (Table 5, Page 5), with no stated upper limit. However, stability analysis in Applications Information (Page 18) recommends X7R/X5R dielectrics and warns against Y5V/Z5U types due to DC bias degradation. Practical designs typically use 1–10 µF; exceeding 22 µF may affect transient response without compensating ESR.

How does the MODE pin affect efficiency across load conditions for ADP5033ACBZ-4-R7?

When MODE = low, ADP5033ACBZ-4-R7 enters power-save mode (PSM) below 100 mA load, reducing switching frequency and quiescent current to maintain >85% efficiency at 1 mA (Fig. 9–10). At MODE = high, forced PWM sustains constant 3 MHz operation, optimizing heavy-load efficiency (>90% at 500 mA) but degrading light-load efficiency to ~60%. This trade-off is explicit in Figure 15–17.