Analog Devices Inc. ADP5033ACBZ-5-R7
- Part No.:
- ADP5033ACBZ-5-R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WFBGA, WLCSP
- Datasheet:
-
ADP5033ACBZ-5-R7.pdf
- Description:
- IC REG QUAD BCK/LNR SYNC 16WLCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP5033ACBZ-5-R7 from Analog Devices is a dual-buck + dual-LDO power management IC integrating two 800 mA, 3 MHz synchronous buck regulators and two 300 mA low-noise LDOs in a 2 mm × 2 mm, 16-ball WLCSP package. It delivers ±1.8% output voltage accuracy, supports factory-programmed VOUT settings, and operates across 2.3 V–5.5 V input for bucks and 1.7 V–5.5 V for LDOs - ideal for space-constrained FPGA/ASIC core-and-I/O rail sequencing.
For engineers reviewing the ADP5033ACBZ-5-R7 datasheet, ADP5033ACBZ-5-R7 pinout, ADP5033ACBZ-5-R7 application, or ADP5033ACBZ-5-R7 equivalent, key selection criteria include out-of-phase buck operation to reduce input ripple, auto PWM/PSM mode switching at 100 mA threshold, high PSRR (>60 dB @ 10 kHz) on LDOs, and independent ENA/ENB enable control with factory-defined channel mapping.
Technical Context
The ADP5033ACBZ-5-R7 implements two independent buck regulators with integrated PFET/NFET switches (RPFET = 145–295 mΩ, RNFET = 110–220 mΩ), fixed 3 MHz switching frequency (2.5–3.5 MHz range), and forced PWM or auto PWM/PSM mode controlled by the MODE pin. Buck1 and Buck2 operate 180° out of phase to minimize input capacitor RMS current and system noise.
Its dual LDOs feature ultra-low dropout (50 mV @ 5.2 V/300 mA), bias current as low as 10 µA at zero load, and PSRR >60 dB up to 1 MHz. Each LDO accepts separate input supplies (VIN3/VIN4) with independent enable (ENB-configured), and maintains regulation over −40°C to +125°C junction temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 800 mA per channel - supports processor core rails and high-current peripherals without external boost stages. |
| LDO Output Current | 300 mA per channel - sufficient for analog sensor biasing, RF front-end I/O, or low-noise ADC/DAC supplies. |
| Switching Frequency | 3 MHz nominal (2.5–3.5 MHz) - enables use of compact 1 µH inductors and 10 µF ceramic output capacitors. |
| Output Voltage Accuracy | ±1.8% - ensures stable logic-level compliance for 1.2 V, 1.8 V, 3.3 V, and other common digital/analog rails. |
| LDO Dropout Voltage | 50 mV @ 5.2 V/300 mA - maximizes battery runtime in single-cell Li-ion (3.0–4.2 V) systems powering 2.8–3.3 V loads. |
| PSRR (LDO) | 60 dB @ 10 kHz, 63 dB @ 1 MHz - suppresses switching noise from adjacent bucks or noisy system rails. |
| Quiescent Current | 108–175 µA (all channels enabled, no switching) - extends standby time in always-on IoT edge nodes. |
Pinout & Package
Tiny 16-ball, 0.5 mm pitch Wafer-Level Chip Scale Package (WLCSP), 2 mm × 2 mm footprint, bottom-side ball layout optimized for minimal PCB area and thermal resistance (θJA = 57°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUT3 | LDO1 output & feedback sense | Provides regulated output and closes feedback loop; requires direct connection to LDO1 output capacitor. |
| VIN3 | LDO1 input supply | Accepts 1.7–5.5 V input; must be ≥ VOUT3 + 0.5 V for full dropout margin. |
| VIN4 | LDO2 input supply | Independent input for LDO2; decoupling required per Table 5 (≥1 µF). |
| VOUT4 | LDO2 output & feedback sense | Regulated output node; used for analog subsystems requiring low noise and high PSRR. |
| AGND | Analog ground reference | Separate ground for LDO feedback and internal error amplifiers; must tie to quiet analog ground plane. |
| MODE | Buck operating mode control | High = forced PWM (constant frequency); Low = auto PWM/PSM (efficiency-optimized below 100 mA). |
| ENA / ENB | Regulator enable inputs | Active-high pins; factory-programmed to control specific buck/LDO channels - not user-reconfigurable. |
| VIN1 / VIN2 | Buck1/Buck2 input supplies | 2.3–5.5 V inputs; must be connected together per datasheet recommendation to ensure UVLO coordination. |
| VOUT1 / VOUT2 | Buck1/Buck2 feedback inputs | Resistive divider connection points; set nominal output voltage (0.8–3.8 V) via external resistor ratios. |
| SW1 / SW2 | Buck switching nodes | Connect to external inductor; require low-ESR ceramic caps (10 µF min) and careful high-frequency layout. |
| PGND1 / PGND2 | Dedicated power grounds | Separate ground returns for each buck stage to prevent coupling; must connect to main GND near input caps. |
Key Features
| Feature | Design Value |
|---|---|
| Out-of-phase buck operation | Reduces input capacitor RMS current by ~30%, enabling smaller 4.7 µF input caps instead of 10 µF+. |
| Factory-programmed VOUT | Eliminates external feedback resistors for standard voltages (e.g., 1.2 V, 1.8 V, 3.3 V), saving board space and BOM cost. |
| Ultra-low LDO quiescent current | 10 µA per LDO at zero load - critical for battery-powered medical sensors with multi-week sleep cycles. |
| High PSRR across frequency | 60–64 dB from 10 kHz to 1 MHz - maintains clean analog supply even when sharing noisy system rail with bucks. |
| Thermal shutdown with hysteresis | 150°C trip with 20°C hysteresis - prevents latch-up during transient overload while allowing safe recovery. |
Applications
| Processor Power Delivery | FPGA Core & I/O Rails |
|---|---|
|
Use Scenario: Powering ARM Cortex-A series SoCs with split-core (VDD_ARM) and I/O (VDD_IO) domains requiring independent voltage scaling and sequencing. IC Role / Device Role / Timing Role: ADP5033ACBZ-5-R7 provides tightly regulated 1.1 V core and 3.3 V I/O rails with <250 µs startup time and coordinated enable control via ENA/ENB. Use Value: Factory-set VOUT eliminates external resistor networks; out-of-phase bucks reduce input ripple, easing EMI filtering requirements. |
Use Scenario: Supplying Xilinx Artix-7 FPGA banks with mixed-voltage I/O (1.2 V, 1.8 V, 3.3 V) and 1.0 V core, where LDO noise sensitivity demands clean auxiliary rails. IC Role / Device Role / Timing Role: ADP5033ACBZ-5-R7's LDO1/LDO2 deliver low-noise 1.2 V and 1.8 V I/O supplies with >60 dB PSRR, while bucks handle high-current core rails. Use Value: Integrated solution replaces discrete buck + LDO combos, cutting PCB area by >40% versus SOT-23-based alternatives. |
| Portable Medical Sensors | Space-Constrained IoT Nodes |
|
Use Scenario: Powering ECG front-end ASICs and Bluetooth LE radios in wearable patches where battery life and EMI are critical. IC Role / Device Role / Timing Role: ADP5033ACBZ-5-R7 supplies 3.3 V analog signal chain (LDO1), 1.8 V digital logic (LDO2), and 1.2 V RF transceiver (Buck2) with <175 µA quiescent current in shutdown. Use Value: 2 mm × 2 mm WLCSP fits inside 8 mm × 8 mm wearable PCBs; PSM mode extends coin-cell life beyond 12 months. |
Use Scenario: Enabling ultra-small form factor environmental monitors (temp/humidity/pressure) with LoRaWAN connectivity and multi-year battery life. IC Role / Device Role / Timing Role: ADP5033ACBZ-5-R7 powers MCU (Buck1), sensor interface (LDO1), radio PA bias (LDO2), and flash memory (Buck2) from single 3.6 V Li-SOCl₂ cell. Use Value: 50 mV dropout at 300 mA allows full utilization of battery voltage down to 2.8 V, adding >15% usable capacity vs. higher-dropout regulators. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-buck + dual-LDO power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5037ACPZ-5-R7 | LFCSP-24 package (4 mm × 4 mm), higher thermal performance (θJA = 42°C/W), same electrical specs. | Better suited for thermally demanding industrial applications with sustained 800 mA loads. | Select when board layout allows larger footprint and thermal relief is prioritized over miniaturization. |
| ADP5134ACPZ-1-R7 | 1.2 A bucks (vs. 800 mA), adds precision enable thresholds and power-good outputs; LDOs unchanged. | Required for higher-current processors (e.g., i.MX 8M Nano) needing >1 A core rails and system-level fault monitoring. | Choose when design requires PG assertion, tighter enable voltage tolerance (±1%), or future-proofing for higher-power SoCs. |
Compared with ADP5033ACBZ-5-R7, ADP5037ACPZ-5-R7 trades size for thermal headroom in continuous high-load scenarios, while ADP5134ACPZ-1-R7 upgrades current capability and adds system-monitoring features - neither offers pin compatibility, but both share identical functional partitioning and enable logic architecture.
Availability
ADP5033ACBZ-5-R7 is available at Aetrix Electronics and suitable for portable instrumentation, medical wearables, and space-constrained IoT nodes requiring stable component supply, long-term lifecycle support, and guaranteed WLCSP packaging consistency.
Supply support for ADP5033ACBZ-5-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, serving industrial, automotive, communications, and healthcare markets.
The ADP5033ACBZ-5-R7 belongs to Analog Devices' µPMU (micropower management unit) product line, engineered specifically for ultra-compact, high-efficiency power delivery in battery-operated and space-limited electronic systems.
FAQ
What is the maximum supported input voltage for the buck regulators in ADP5033ACBZ-5-R7?
The ADP5033ACBZ-5-R7 buck regulators (BUCK1 and BUCK2) accept an input voltage range of 2.3 V to 5.5 V. This is specified under "INPUT CHARACTERISTICS" in Table 3 of the Rev. H datasheet. Operation above 5.5 V violates absolute maximum ratings and may cause permanent damage. VIN1 and VIN2 must be tied together per recommended application circuit.
Does ADP5033ACBZ-5-R7 support independent voltage programming for each regulator channel?
Yes - ADP5033ACBZ-5-R7 supports factory-programmed output voltages for all four channels (BUCK1, BUCK2, LDO1, LDO2) within their respective ranges: 0.8 V–3.8 V for bucks and 0.8 V–5.2 V for LDOs. This eliminates external feedback resistors for standard voltages, though resistor-based adjustment remains possible via VOUT1/VOUT2 and VOUT3/VOUT4 pins.
How does the MODE pin affect efficiency in ADP5033ACBZ-5-R7 under light load conditions?
When the MODE pin is low, ADP5033ACBZ-5-R7 enters auto PWM/PSM mode: it operates in PWM above ~100 mA load and switches to power-save mode (PSM) below that threshold. This improves light-load efficiency significantly - e.g., Figure 9 shows >85% efficiency at 1 mA for VOUT1 = 3.3 V in auto mode, versus ~60% in forced PWM.
Can ADP5033ACBZ-5-R7 LDOs operate with input-to-output differentials below 100 mV?
Yes - ADP5033ACBZ-5-R7 LDOs achieve dropout voltages as low as 50 mV (at 5.2 V/300 mA) and 65 mV (at 3.3 V/300 mA), per Table 4. This enables operation with sub-100 mV headroom in high-efficiency battery systems, provided VIN3/VIN4 ≥ VOUT3/VOUT4 + 0.5 V minimum for guaranteed regulation.
What is the thermal resistance (θJA) of ADP5033ACBZ-5-R7 in its WLCSP package?
The ADP5033ACBZ-5-R7 in its 16-ball, 2 mm × 2 mm WLCSP package has a junction-to-ambient thermal resistance (θJA) of 57°C/W, as specified in Table 7 of the Rev. H datasheet. This value assumes worst-case PCB mounting per JEDEC J-STD-020; actual performance improves with enhanced copper pour and thermal vias.
ADP5033ACBZ-5-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- 3.3V, 800mA
- Voltage/Current - Output 2:
- 1.8V, 800mA
- Voltage/Current - Output 3:
- 1.2V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WLCSP (2x2)
ADP5033ACBZ-5-R7 FAQ
1.How can I place an order for ADP5033ACBZ-5-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5033ACBZ-5-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5033ACBZ-5-R7 reliable?
The price and inventory of ADP5033ACBZ-5-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5033ACBZ-5-R7 is usually 5 days.
3.What payment methods are accepted for ADP5033ACBZ-5-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5033ACBZ-5-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5033ACBZ-5-R7?
ADP5033ACBZ-5-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5033ACBZ-5-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5033ACBZ-5-R7?
For technical support, including ADP5033ACBZ-5-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5033ACBZ-5-R7 requirements.
6.How does Aetrix verify that ADP5033ACBZ-5-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5033ACBZ-5-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5033ACBZ-5-R7 meets industry standards.
7.What is the process for return or replacement of ADP5033ACBZ-5-R7?
All ADP5033ACBZ-5-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5033ACBZ-5-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5033ACBZ-5-R7 part is unused and in its original packaging.
Return procedure for ADP5033ACBZ-5-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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