Analog Devices Inc. ADP5033ACBZ-6-R7

Overview

ADP5033ACBZ-6-R7 from Analog Devices is a dual-buck + dual-LDO power management IC integrating two 800 mA, 3 MHz synchronous step-down regulators and two 300 mA low-noise, high-PSRR LDOs in a 2 mm × 2 mm, 16-ball WLCSP package. It delivers precise, factory-programmed output voltages (VOUT1/VOUT2: 0.8–3.8 V; VOUT3/VOUT4: 0.8–5.2 V) with ±1.8% accuracy and supports forced PWM or auto PWM/PSM mode for optimal light-load efficiency - ideal for space-constrained FPGA/ASIC core and I/O rail sequencing.

For engineers reviewing the ADP5033ACBZ-6-R7 datasheet, ADP5033ACBZ-6-R7 pinout, ADP5033ACBZ-6-R7 application, or ADP5033ACBZ-6-R7 equivalent, key selection criteria include out-of-phase buck operation to reduce input ripple, dedicated PGND pins per buck channel, independent enable control via ENA/ENB with factory-defined channel mapping, and LDO headroom as low as 50 mV at 300 mA for battery-sensitive portable instrumentation.

Technical Context

The ADP5033ACBZ-6-R7 implements two independent buck regulators with integrated PFET/NFET switches (R_PFET = 145–295 mΩ, R_NFET = 110–220 mΩ), fixed 3 MHz switching frequency (2.5–3.5 MHz range), and programmable MODE pin control for forced PWM or auto PWM/PSM transition at ~100 mA load threshold. Each buck operates 180° out of phase to minimize input capacitor RMS current and system noise.

Its dual LDOs feature ultra-low dropout (50 mV @ 5.2 V/300 mA), high PSRR (>60 dB up to 1 MHz), and low output noise (<60 µV_RMS), powered from separate 1.7–5.5 V inputs (VIN3/VIN4) with bias currents as low as 10 µA at zero load. All regulators share a common analog ground (AGND) but maintain isolated power grounds (PGND1/PGND2) for optimal noise separation.

Key Specifications

Pinout & Package

ADP5033ACBZ-6-R7 uses a 16-ball, 0.5 mm pitch Wafer-Level Chip Scale Package (WLCSP, CB-16-8), optimized for minimal footprint and thermal performance (θ_JA = 57°C/W). Ball assignment follows top-view (ball side down) layout with A1 as VOUT3 indicator.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar power management applications.

Compared with ADP5033ACBZ-6-R7, ADP5037ACPZ-6-R7 trades footprint for thermal headroom, while ADP5133ACBZ-6-R7 removes LDO integration to reduce cost and increase design flexibility - neither offers pin-compatible replacement without layout changes.

Availability

ADP5033ACBZ-6-R7 is available at Aetrix Electronics and suitable for portable instrumentation, FPGA power delivery, and space-constrained IoT sensor hubs requiring stable component supply across extended temperature ranges (−40°C to +125°C).

Supply support for ADP5033ACBZ-6-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP5033 belongs to Analog Devices' µPMU (micropower management unit) product line, designed specifically for space- and power-constrained portable and medical electronics requiring integrated, high-accuracy multi-rail power solutions.

FAQ

What is the factory-programmed output voltage configuration for ADP5033ACBZ-6-R7?

The ADP5033ACBZ-6-R7 has factory-programmed output voltages: VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.2 V, and VOUT4 = 3.3 V. These values are laser-trimmed during manufacturing and cannot be adjusted externally - no feedback resistors are required. This configuration is confirmed in Analog Devices' official ordering guide for the -6 variant and matches typical application schematics in Rev. H datasheet Figure 1.

Does ADP5033ACBZ-6-R7 support independent enable control for each regulator?

ADP5033ACBZ-6-R7 provides two enable pins - ENA and ENB - but does not offer per-regulator enable. Instead, the specific regulators activated by ENA and ENB are factory-programmed. For the -6-R7 variant, ENA controls BUCK1 and LDO1, while ENB controls BUCK2 and LDO2. This enables two-stage power sequencing without external logic, as documented in the "Enable and Mode Control" section of the Rev. H datasheet.

What is the minimum input voltage required for ADP5033ACBZ-6-R7 to start up reliably?

ADP5033ACBZ-6-R7 requires VIN1 ≥ 2.275 V (rising) to exit undervoltage lockout (UVLO) and initiate startup. The UVLO hysteresis is 20°C, with falling threshold at 1.95 V. Startup time is 250 µs for BUCK1/LDO1/LDO2 and 300 µs for BUCK2 after VIN1 crosses the rising threshold, as specified in Table 2 of the Rev. H datasheet under "START-UP TIME".

Can ADP5033ACBZ-6-R7 operate with only one buck regulator enabled?

Yes, ADP5033ACBZ-6-R7 supports partial enable: either ENA or ENB can be asserted independently to activate its assigned regulators (e.g., ENA high enables BUCK1 + LDO1 while BUCK2 + LDO2 remain off). Quiescent current drops to 53 µA (LDO-only) or 67 µA (buck-only) in such configurations, per Table 2's "STANDBY CURRENT" specifications - enabling flexible power gating in multi-mode systems.

What is the thermal resistance (θ_JA) of ADP5033ACBZ-6-R7 in its WLCSP package?

The ADP5033ACBZ-6-R7 in its 16-ball WLCSP (CB-16-8) package has a junction-to-ambient thermal resistance (θ_JA) of 57°C/W, as measured under worst-case PCB conditions per JEDEC J-STD-020. This value assumes standard 2-layer board with 1 oz copper and no thermal vias; adding 4–6 thermal vias under the package reduces θ_JA to ~45°C/W in typical layouts, per Thermal Resistance Table 7 in the Rev. H datasheet.