Analog Devices Inc. ADP5033ACBZ-7-R7

Overview

ADP5033ACBZ-7-R7 from Analog Devices is a dual-buck + dual-LDO power management IC in a 2 mm × 2 mm WLCSP package, delivering two 800 mA synchronous buck regulators (3 MHz switching) and two 300 mA low-noise LDOs with ±1.8% output accuracy, factory-programmable VOUT, and independent enable control - designed for space-constrained portable processors and RF chipsets.

For engineers reviewing the ADP5033ACBZ-7-R7 datasheet, ADP5033ACBZ-7-R7 pinout, ADP5033ACBZ-7-R7 application, or ADP5033ACBZ-7-R7 equivalent, this page provides verified regulator accuracy, out-of-phase buck operation, PSRR >60 dB at 10 kHz, thermal shutdown at 150°C, and confirmed WLCSP-16 ball mapping per Rev. H datasheet.

Technical Context

The ADP5033ACBZ-7-R7 integrates two independent buck converters operating out of phase to reduce input ripple and capacitor requirements, each supporting forced PWM or auto PWM/PSM mode via the MODE pin. BUCK1 and BUCK2 share no internal coupling but are synchronized to minimize EMI and improve transient response under dynamic load conditions.

Its dual LDOs feature low dropout (e.g., 65 mV @ 3.3 V/300 mA), high PSRR (>60 dB up to 1 MHz), and separate input rails (VIN3/VIN4) with 1.7 V–5.5 V range - enabling analog/digital domain isolation. Factory-programmed ENA/ENB pin assignments determine which regulators activate per enable signal.

Key Specifications

Pinout & Package

ADP5033ACBZ-7-R7 uses a 16-ball, 0.5 mm pitch Wafer-Level Chip Scale Package (WLCSP), optimized for minimal PCB footprint and thermal performance (θJA = 57°C/W). Ball assignment follows top-view die-down orientation with A1 as VOUT3 indicator.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buck + dual-LDO power management applications.

Compared with ADP5033ACBZ-7-R7, ADP5037ACPZ-2-R7 offers identical regulation performance in a thermally robust LFCSP package but increases PCB area by 4×; ADP5134ACPZ-2-R7 trades factory-programmed simplicity for higher current and system-level monitoring features - neither is pin-compatible, requiring full layout revision.

Availability

ADP5033ACBZ-7-R7 is available at Aetrix Electronics and suitable for mobile baseband processors, FPGA power delivery, portable medical sensors, and RF front-end modules requiring stable component supply, long-term lifecycle support, and guaranteed WLCSP-16 sourcing.

Supply support for ADP5033ACBZ-7-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and power management semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The ADP5033ACBZ-7-R7 belongs to Analog Devices' µPMU (micropower management unit) product line, engineered specifically for space-constrained portable electronics requiring integrated, high-efficiency, low-noise multi-rail power solutions.

FAQ

What is the maximum supported output current for each regulator in ADP5033ACBZ-7-R7?

ADP5033ACBZ-7-R7 supports up to 800 mA per buck regulator (BUCK1 and BUCK2) and up to 300 mA per LDO (LDO1 and LDO2), as specified in the Rev. H datasheet under BUCK1/BUCK2 and LDO1/LDO2 Specifications tables. These values are validated across −40°C to +125°C junction temperature with appropriate PCB thermal design.

Does ADP5033ACBZ-7-R7 support independent voltage programming for all four outputs?

Yes - ADP5033ACBZ-7-R7 supports factory-programmable VOUT for all four outputs: BUCK1 and BUCK2 range from 0.8 V to 3.8 V; LDO1 and LDO2 range from 0.8 V to 5.2 V. Programming is performed at wafer sort and cannot be modified in-circuit; external resistor dividers are optional only for non-standard voltages.

How does the MODE pin affect efficiency in ADP5033ACBZ-7-R7?

When MODE = high, ADP5033ACBZ-7-R7 operates in forced PWM mode - maintaining constant 3 MHz switching regardless of load, optimizing heavy-load efficiency. When MODE = low, it switches automatically to PSM at light loads (<100 mA), reducing quiescent current and improving efficiency below 10% load - critical for battery longevity.

What is the purpose of separate AGND and PGND pins in ADP5033ACBZ-7-R7?

ADP5033ACBZ-7-R7 separates AGND (analog ground) from PGND1/PGND2 (power grounds) to isolate sensitive LDO feedback paths from high-di/dt buck switching currents. Routing AGND to a quiet ground plane - distinct from noisy power ground pours - preserves LDO output accuracy and PSRR performance per Rev. H Layout Guidelines.

Can ADP5033ACBZ-7-R7 operate with input voltages below 2.3 V?

No - ADP5033ACBZ-7-R7's buck regulators require VIN1/VIN2 ≥ 2.3 V per Absolute Maximum Ratings and General Specifications. However, its LDOs accept VIN3/VIN4 as low as 1.7 V (provided headroom ≥0.5 V above VOUT), enabling partial operation from lower-voltage sources when bucks are disabled.