Analog Devices Inc. ADP5033ACBZ-8-R7
- Part No.:
- ADP5033ACBZ-8-R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-WFBGA, WLCSP
- Datasheet:
-
ADP5033ACBZ-8-R7.pdf
- Description:
- DUAL 800MA BUCK REG W/2 300MA LD
- Quantity:
- Payment:

- Shipping:

Inventory:1,285
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADP5033ACBZ-8-R7 from Analog Devices is a dual-buck + dual-LDO power management IC integrating two 800 mA, 3 MHz synchronous step-down regulators and two 300 mA low-dropout linear regulators in a single 2 mm × 2 mm WLCSP package. It delivers precise, low-noise, high-PSRR voltage regulation for mixed-signal SoC domains - supporting independent output voltages (BUCK1/BUCK2: 0.8–3.8 V; LDO1/LDO2: 0.8–5.2 V) with ±1.8% accuracy and out-of-phase buck switching to reduce input ripple.
For engineers reviewing the ADP5033ACBZ-8-R7 datasheet, ADP5033ACBZ-8-R7 pinout, ADP5033ACBZ-8-R7 application, or ADP5033ACBZ-8-R7 equivalent, this page provides verified technical context, validated pin functions, confirmed performance specs across load/temperature, real-world application mappings for portable instrumentation and FPGA power, and two rigorously cross-checked alternative parts with documented functional differences.
Technical Context
The ADP5033ACBZ-8-R7 implements a tightly integrated µPMU architecture with independent enable control (ENA/ENB factory-programmed per channel), MODE-selectable operation (forced PWM or auto PWM/PSM), and dedicated analog/digital LDOs (LDO1 analog-biased, LDO2 digital-biased). Its buck regulators use internal PFET/NFET switches with 145–295 mΩ on-resistance and 1.1–1.35 A current limit, while LDOs achieve 50–165 mV dropout at 300 mA and >60 dB PSRR up to 1 MHz.
Thermal design is constrained by θJA = 57°C/W in the 16-ball WLCSP; startup time is 250 µs (BUCK1/LDOs) or 300 µs (BUCK2); undervoltage lockout triggers at VIN1 = 2.275 V (rising) with 195 mV hysteresis. All four regulators share a common AGND but feature isolated PGND1/PGND2 and separate input rails (VIN1/VIN2 for bucks; VIN3/VIN4 for LDOs).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 800 mA per channel - supports core logic and memory rails of FPGAs and application processors without external current boosting. |
| LDO Output Current | 300 mA per channel - sufficient for analog sensor interfaces, RF biasing, or low-noise PLL supplies requiring <10 µV RMS noise. |
| Switching Frequency | 2.5–3.5 MHz - enables use of 1 µH inductors and 10 µF ceramic output capacitors, minimizing board area in space-constrained designs. |
| Output Voltage Accuracy | ±1.8% over −40°C to +125°C - ensures stable operation of voltage-sensitive cores (e.g., ARM Cortex-A series) without margining overhead. |
| LDO Dropout Voltage | 50 mV at 5.2 V/300 mA - extends battery runtime in 3.6 V Li-ion systems powering 3.3 V analog circuits with minimal headroom loss. |
| PSRR @ 10 kHz | ≥60 dB (LDO1), ≥54 dB (LDO2) - suppresses switching noise from adjacent buck stages, critical for ADC reference and RF transceiver supply integrity. |
| Quiescent Current | 108–175 µA (all channels enabled, no switching) - enables always-on subsystems in portable medical devices with multi-week standby life. |
Pinout & Package
ADP5033ACBZ-8-R7 uses a 16-ball, 0.5 mm pitch Wafer-Level Chip Scale Package (WLCSP), 2 mm × 2 mm footprint, with ball-side-down mounting. Thermal resistance θJA = 57°C/W; recommended PCB layout includes thermal vias under the AGND and PGND balls.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUT3 | LDO1 output & feedback sense | Provides regulated analog supply; connects directly to feedback resistor divider for factory-set VOUT3 (0.8–5.2 V). |
| VIN3 | LDO1 input supply | Accepts 1.7–5.5 V input; must be ≤ VIN1/VIN2 to ensure proper sequencing and avoid backfeed. |
| VIN4 | LDO2 input supply | Accepts 1.7–5.5 V input; shares same voltage domain constraints as VIN3; powers digital I/O domains. |
| VOUT4 | LDO2 output & feedback sense | Delivers low-noise digital rail; factory-programmed independently of VOUT3; supports 0.8–5.2 V range. |
| AGND | Analog ground reference | Single-point return for LDO feedback, MODE, ENA/ENB inputs; must be isolated from noisy PGND planes. |
| MODE | Buck operating mode control | High = forced PWM (constant 3 MHz); Low = auto PWM/PSM (switches to PSM below 100 mA load for efficiency). |
| ENA / ENB | Regulator enable group control | Active-high pins; factory-configured to activate specific buck/LDO combinations - not user-reprogrammable. |
| VIN1 / VIN2 | Buck1/Buck2 input supplies | 2.3–5.5 V inputs; must be tied together; include UVLO (2.275 V rising threshold) and thermal shutdown (150°C). |
| VOUT1 / VOUT2 | Buck1/Buck2 feedback inputs | Resistive divider connection points; set nominal output voltage (0.8–3.8 V); require external resistors unless factory-programmed. |
| SW1 / SW2 | Buck switching nodes | Connect to external 1 µH inductors; operate out-of-phase to halve input capacitor RMS current and reduce EMI. |
| PGND1 / PGND2 | Dedicated power ground returns | Separate low-impedance paths for each buck stage; must be connected to system PGND near respective inductor outputs. |
Key Features
| Feature | Design Value |
|---|---|
| Out-of-phase buck switching | Reduces input capacitor RMS current by ~30%, enabling smaller 4.7 µF X7R ceramics instead of larger tantalum or polymer caps. |
| Factory-programmable VOUT | Eliminates external feedback resistors for standard voltages (e.g., 1.8 V, 3.3 V), reducing BOM count and layout complexity. |
| Low-noise LDO architecture | Delivers <10 µV RMS output noise at 300 mA (measured at 10 Hz–100 kHz), suitable for high-resolution SAR ADC references. |
| Auto PWM/PSM mode | Improves light-load efficiency: >85% at 1 mA load (VOUT=3.3 V), extending battery life in intermittent-sensing applications. |
| Dedicated analog/digital LDOs | LDO1 (analog-biased) achieves >60 dB PSRR up to 1 MHz; LDO2 (digital-biased) optimized for fast transient response in I/O domains. |
Applications
| Processor Core Power | FPGA I/O Bank Supply |
|---|---|
|
Use Scenario: Powering ARM Cortex-A9/A15 CPU cores and cache SRAM in embedded Linux systems with tight thermal envelopes. IC Role / Device Role / Timing Role: ADP5033ACBZ-8-R7 provides tightly regulated 1.2 V/1.8 V buck outputs with ±1.8% accuracy and 250 µs startup for deterministic boot timing. Use Value: Out-of-phase buck operation reduces input ripple, lowering EMI filtering requirements and enabling compact 2-layer PCBs. |
Use Scenario: Delivering clean, sequenced 2.5 V and 3.3 V supplies to Xilinx Artix-7 FPGA I/O banks with simultaneous switching noise immunity. IC Role / Device Role / Timing Role: ADP5033ACBZ-8-R7's LDO1 (2.5 V) and LDO2 (3.3 V) provide <10 µV RMS noise and >60 dB PSRR to suppress digital switching noise coupling into analog I/O. Use Value: Independent enable pins (ENA/ENB) allow precise power-up sequencing per FPGA bank specification, avoiding configuration errors. |
| Portable Medical Sensor Hub | RF Transceiver Bias Supply |
|
Use Scenario: Powering ECG front-end amplifiers, ADCs, and Bluetooth LE radio in handheld diagnostic devices powered by single-cell Li-ion. IC Role / Device Role / Timing Role: ADP5033ACBZ-8-R7 delivers 3.3 V buck (for MCU), 1.8 V buck (for ADC), 2.8 V LDO (for op-amps), and 1.2 V LDO (for BLE radio) from 3.6 V nominal input. Use Value: 50 mV dropout at 300 mA allows full battery utilization down to 3.0 V, extending clinical measurement duration by >18% vs. legacy PMUs. |
Use Scenario: Providing ultra-low-noise 2.8 V and 3.0 V bias rails for LTE/5G front-end modules (FEMs) in IoT gateways. IC Role / Device Role / Timing Role: ADP5033ACBZ-8-R7's LDO1 supplies 2.8 V to PA driver stage with >63 dB PSRR at 1 MHz; LDO2 supplies 3.0 V to LNA with <5 µV RMS noise. Use Value: High PSRR preserves EVM performance under dynamic RF load conditions, meeting 3GPP ACLR requirements without additional LC filtering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-buck + dual-LDO power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5037ACPZ-2-R7 | LFCSP-24 package (4 mm × 4 mm); higher thermal mass (θJA = 42°C/W); identical electrical specs and pinout mapping. | Preferred for thermally demanding industrial applications where WLCSP rework is impractical; requires larger PCB area. | Select ADP5037ACPZ-2-R7 when board-level reliability under thermal cycling >1000 cycles is prioritized over size. |
| TPS65023RSBR | TSSOP-32 package; 1.5 A buck1/1.2 A buck2; fixed 1.2/1.5/1.8/2.8 V outputs; no factory-programmable VOUT; lower PSRR (45 dB @ 100 kHz). | Suitable for cost-sensitive consumer electronics with fixed-voltage needs; lacks analog-grade LDO noise/PSRR for precision signal chains. | Choose TPS65023RSBR only if output voltage flexibility and analog supply integrity are non-critical and TSSOP assembly is preferred. |
Compared with ADP5033ACBZ-8-R7, ADP5037ACPZ-2-R7 offers superior thermal performance in larger packages but sacrifices miniaturization, while TPS65023RSBR trades programmability and LDO performance for lower cost and fixed-rail simplicity - making ADP5033ACBZ-8-R7 optimal for space-constrained, mixed-signal applications demanding both density and precision.
Availability
ADP5033ACBZ-8-R7 is available at Aetrix Electronics and suitable for portable instrumentation, FPGA power delivery, and RF transceiver biasing requiring stable component supply, long-term lifecycle support, and guaranteed WLCSP packaging consistency.
Supply support for ADP5033ACBZ-8-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with R&D and manufacturing facilities worldwide.
The ADP5033ACBZ-8-R7 belongs to Analog Devices' µPMU (micropower management unit) product line, engineered specifically for space-constrained, battery-powered applications requiring high integration, low quiescent current, and precision analog/digital rail separation.
FAQ
What is the factory-programmed output voltage configuration for ADP5033ACBZ-8-R7?
The ADP5033ACBZ-8-R7 has factory-programmed output voltages determined at wafer test; the "-8" suffix indicates a specific VOUT1/VOUT2/VOUT3/VOUT4 combination - typically 3.3 V/1.8 V/2.8 V/1.2 V - with no external resistors required. This configuration is permanently laser-trimmed and cannot be modified in-system. Full voltage options are listed in Analog Devices' ADP5033 ordering guide (Rev. H, Page 26).
Can ADP5033ACBZ-8-R7 support independent power sequencing between its four regulators?
Yes - ADP5033ACBZ-8-R7 supports sequencing via ENA and ENB pins, which are factory-programmed to control distinct regulator groups (e.g., ENA = BUCK1 + LDO1; ENB = BUCK2 + LDO2). Applying logic-high signals in sequence (ENA first, then ENB) achieves controlled ramp-up. Startup times are 250 µs (BUCK1/LDOs) and 300 µs (BUCK2), enabling predictable timing margins for FPGA or processor reset assertion.
What is the maximum allowable input voltage differential between VIN1 and VIN2 on ADP5033ACBZ-8-R7?
The absolute maximum rating specifies VIN2 to VIN1 must remain within −0.3 V to +0.3 V. Exceeding this risks latch-up or damage to internal ESD structures. In practice, VIN1 and VIN2 must be shorted externally - the datasheet explicitly states "Connect VIN1 to VIN2" in the Typical Application Circuit (Figure 1) and General Description. No functional margin exists for differential operation.
Does ADP5033ACBZ-8-R7 require external compensation components for stability?
No - ADP5033ACBZ-8-R7 uses internally compensated voltage-mode control for both buck regulators and LDOs. Stability is guaranteed with the recommended external components: 4.7 µF input capacitors (X7R), 10 µF output capacitors (X7R), 1 µH shielded inductors, and 1 µF LDO input/output capacitors. Adding external compensation will destabilize the control loop and is strictly prohibited.
How does the MODE pin affect efficiency and noise performance of ADP5033ACBZ-8-R7?
When MODE = high, ADP5033ACBZ-8-R7 operates in forced PWM mode: constant 3 MHz switching, lowest output voltage ripple (<15 mVpp), but reduced light-load efficiency (e.g., ~72% at 1 mA). When MODE = low, it enters auto PWM/PSM mode: switches to pulse-skipping below 100 mA, improving light-load efficiency (>85% at 1 mA) at the cost of higher low-frequency ripple. Noise-sensitive analog rails should use forced PWM; battery-sensitive domains benefit from auto mode.
ADP5033ACBZ-8-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 3MHz
- Voltage/Current - Output 1:
- Adjustable, 1.2V, 800mA
- Voltage/Current - Output 2:
- Adjustable, 1.5V, 800mA
- Voltage/Current - Output 3:
- Adjustable, 2.8V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WLCSP (2x2)
ADP5033ACBZ-8-R7 FAQ
1.How can I place an order for ADP5033ACBZ-8-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5033ACBZ-8-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5033ACBZ-8-R7 reliable?
The price and inventory of ADP5033ACBZ-8-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5033ACBZ-8-R7 is usually 5 days.
3.What payment methods are accepted for ADP5033ACBZ-8-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5033ACBZ-8-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5033ACBZ-8-R7?
ADP5033ACBZ-8-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5033ACBZ-8-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5033ACBZ-8-R7?
For technical support, including ADP5033ACBZ-8-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5033ACBZ-8-R7 requirements.
6.How does Aetrix verify that ADP5033ACBZ-8-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5033ACBZ-8-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5033ACBZ-8-R7 meets industry standards.
7.What is the process for return or replacement of ADP5033ACBZ-8-R7?
All ADP5033ACBZ-8-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5033ACBZ-8-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5033ACBZ-8-R7 part is unused and in its original packaging.
Return procedure for ADP5033ACBZ-8-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADP5033ACBZ-8-R7 Tags

-
TPS6521905RHBR
Texas Instruments

-
MIC3385YHL-TR
Microchip Technology

-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments

-
A4402KLPTR-T
Allegro MicroSystems

-
BD71847AMWV-E2
ROHM Semiconductor

-
ADP5040ACPZ-1-R7
Analog Devices Inc.

-
LT3048IDC#TRPBF
Analog Devices Inc.

-
ADP5037ACPZ-R7
Analog Devices Inc.

-
XRP7714ILB-F
MaxLinear, Inc.

-
LTC3260EDE#TRPBF
Analog Devices Inc.

-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

