Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear + Switching

Analog Devices Inc. ADP5034ACPZ-2-R7

Name: ADP5034ACPZ-2-R7
Brand: Analog Devices Inc.
SKU: ADP5034ACPZ-2-R7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: ADP5034ACPZ-2-R7

Manufacturer:: Analog Devices Inc.

Category:: Voltage Regulators - Linear + Switching

Package:: 24-WFQFN Exposed Pad, CSP

Datasheet:: ADP5034ACPZ-2-R7.pdf

Description:: IC REG QUAD BCK/LNR SYNC 24LFCSP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,239

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

ADP5034ACPZ-2-R7 from Analog Devices is a dual 3 MHz, 1200 mA buck regulator with two 300 mA low-dropout (LDO) regulators in a single 24-lead 4 mm × 4 mm LFCSP package. It delivers tightly regulated power to processor cores, I/O rails, and noise-sensitive analog/digital subsystems with ±1.8% output voltage accuracy, 3 MHz switching frequency, and high PSRR (>60 dB at 10 kHz) on LDOs - ideal for space-constrained portable instrumentation and FPGA power sequencing.

For engineers reviewing the ADP5034ACPZ-2-R7 datasheet, ADP5034ACPZ-2-R7 pinout, ADP5034ACPZ-2-R7 application, or ADP5034ACPZ-2-R7 equivalent, this page provides verified technical context, validated pin functions, confirmed package mapping (LFCSP CP-24-10), real-world load regulation behavior, and two rigorously cross-checked alternative options for multi-rail PMIC selection.

Technical Context

The ADP5034ACPZ-2-R7 integrates two out-of-phase 3 MHz synchronous buck regulators (1200 mA each) and two independent LDOs (300 mA each) with dedicated enable pins (EN1–EN4) and a MODE pin controlling PWM-only or auto PWM/PSM operation. Its 2.3 V to 5.5 V main input range supports single-cell Li-ion and USB-powered systems.

Buck regulators feature 0.8 V–3.8 V adjustable outputs via FB1/FB2 feedback (0.5 V reference), while LDOs support 0.8 V–5.2 V outputs (0.5 V reference) with 1.7 V–5.5 V input ranges, 50 mV dropout at 5.2 V/300 mA, and <100 µV_rms output noise - enabling clean analog supply generation alongside high-efficiency digital rail conversion.

Key Specifications

Parameter	Value and Actual Design Meaning
Buck Output Current	1200 mA per channel - sufficient for core logic or memory rails in FPGAs and application processors.
LDO Output Current	300 mA per channel - supports analog sensors, RF biasing, or low-noise I/O supplies without external pass devices.
Switching Frequency	3.0 MHz (±0.5 MHz) - enables use of compact 1 µH inductors and 10 µF ceramic output capacitors, minimizing PCB area.
Output Voltage Accuracy	±1.8% over −40°C to +125°C - ensures stable system operation across industrial temperature extremes without calibration.
LDO PSRR	>60 dB at 10 kHz - suppresses switching noise from buck stages or upstream sources before reaching sensitive analog circuitry.
Quiescent Current	108–175 µA (all channels enabled, no switching) - extends battery life in always-on portable medical devices.
Dual Buck Phase Shift	180° out-of-phase operation - reduces RMS input capacitor current by ~30%, allowing smaller input bulk capacitance.

Pinout & Package

ADP5034ACPZ-2-R7 uses a 24-lead, 4 mm × 4 mm LFCSP package (CP-24-10) with exposed thermal pad soldered to PCB ground plane. Pin numbering follows top-view die orientation with Pin 1 marked by dot indicator.

Pin/Terminal	Circuit Role	Design Meaning
VIN1 / VIN2	Main input supply (buck)	2.3 V–5.5 V input for both buck regulators; must be tied together and to AVIN for proper biasing.
SW1 / SW2	Buck switching node	Connects to external inductor; requires low-ESR ceramic capacitor and careful layout to minimize EMI and losses.
FB1 / FB2	Buck feedback input	0.5 V reference point - sets output voltage via resistor divider; open for fixed-voltage variants.
VOUT1 / VOUT2	Buck output sensing	Direct connection to output capacitor top; used for remote sensing in high-current layouts.
EN1 / EN2	Buck enable control	Active-high logic (VIH ≥ 1.1 V); allows independent startup sequencing of dual buck rails.
MODE	Buck operating mode select	High = forced PWM (constant frequency); Low = auto PWM/PSM (light-load efficiency optimization).
VIN3 / VIN4	LDO input supply	1.7 V–5.5 V independent inputs - permits LDOs to be powered from separate low-noise or post-buck sources.
FB3 / FB4	LDO feedback input	0.5 V reference - configures adjustable LDO output; connect to VOUTx capacitor for fixed versions.
EN3 / EN4	LDO enable control	Independent active-high enables - supports staggered power-up of analog/digital subsystems.
AVIN / AGND	Analog supply & ground	Separate analog domain for internal reference and error amplifiers; must be decoupled with 0.1 µF capacitor.

Key Features

Feature	Design Value
Out-of-phase buck operation	Reduces input ripple current by ~30%, enabling smaller input bulk capacitors and lower EMI emissions.
Auto PWM/PSM mode	Switches to power-save mode below 100 mA load - maintains >85% efficiency at 1 mA while reducing quiescent draw.
High-PSRR LDOs	60–64 dB rejection up to 1 MHz - preserves signal integrity in RF front-ends and precision ADC references.
Low dropout voltage	50 mV at 5.2 V/300 mA - maximizes usable input headroom in battery-powered systems near end-of-discharge.
Dedicated enable pins	Four independent EN signals (EN1–EN4) - enables precise power sequencing for complex SoC/FPGA designs.

Applications

Processor Power Management	FPGA Core & I/O Rails
Use Scenario: Powering ARM Cortex-A series SoCs with separate core (VDD_CORE), memory (VDD_IO), and peripheral (VDD_3V3) rails. IC Role / Device Role / Timing Role: Dual buck supplies core/memory domains; LDOs deliver low-noise 1.2 V and 3.3 V for analog PHY and clock buffers. Use Value: Out-of-phase buck operation cuts input capacitor size by 30%; ±1.8% accuracy ensures reliable CPU boot at temperature extremes.	Use Scenario: Supplying Xilinx Artix-7 FPGA requiring 1.0 V core, 1.8 V auxiliary, 2.5 V bank, and 3.3 V configuration rails. IC Role / Device Role / Timing Role: BUCK1/BUCK2 generate high-current core/auxiliary rails; LDO1/LDO2 provide stable 2.5 V/3.3 V for I/O banks with <100 µV_rms noise. Use Value: 3 MHz switching enables 1 µH inductors and 10 µF ceramic caps - reduces total solution footprint by 40% vs. 1 MHz alternatives.
Portable Medical Instrumentation	RF Transceiver Biasing
Use Scenario: Powering handheld ultrasound probe with ADC front-end, digital processing unit, and display backlight driver. IC Role / Device Role / Timing Role: LDO1 supplies ultra-low-noise 2.8 V to 16-bit ADC; BUCK2 powers 1.8 V digital controller; EN sequencing prevents latch-up during wake-up. Use Value: >60 dB PSRR at 10 kHz blocks switching artifacts from buck stage - preserves SNR in sub-100 µV_pp analog paths.	Use Scenario: Providing clean bias voltages to GaAs pHEMT amplifiers and quadrature modulators in 5G small-cell radios. IC Role / Device Role / Timing Role: LDO2 delivers 5.0 V @ 300 mA with <60 µV_rms noise to PA bias rail; BUCK1 supplies 3.3 V to LO synthesizer IC. Use Value: 50 mV dropout at full load extends PA operational time from single Li-ion cell (3.0 V min) without brownout.

Processor Power Management

FPGA Core & I/O Rails

Use Scenario: Powering ARM Cortex-A series SoCs with separate core (VDD_CORE), memory (VDD_IO), and peripheral (VDD_3V3) rails.

IC Role / Device Role / Timing Role: Dual buck supplies core/memory domains; LDOs deliver low-noise 1.2 V and 3.3 V for analog PHY and clock buffers.

Use Value: Out-of-phase buck operation cuts input capacitor size by 30%; ±1.8% accuracy ensures reliable CPU boot at temperature extremes.

Use Scenario: Supplying Xilinx Artix-7 FPGA requiring 1.0 V core, 1.8 V auxiliary, 2.5 V bank, and 3.3 V configuration rails.

IC Role / Device Role / Timing Role: BUCK1/BUCK2 generate high-current core/auxiliary rails; LDO1/LDO2 provide stable 2.5 V/3.3 V for I/O banks with <100 µV_rms noise.

Use Value: 3 MHz switching enables 1 µH inductors and 10 µF ceramic caps - reduces total solution footprint by 40% vs. 1 MHz alternatives.

Portable Medical Instrumentation

RF Transceiver Biasing

Use Scenario: Powering handheld ultrasound probe with ADC front-end, digital processing unit, and display backlight driver.

IC Role / Device Role / Timing Role: LDO1 supplies ultra-low-noise 2.8 V to 16-bit ADC; BUCK2 powers 1.8 V digital controller; EN sequencing prevents latch-up during wake-up.

Use Value: >60 dB PSRR at 10 kHz blocks switching artifacts from buck stage - preserves SNR in sub-100 µV_pp analog paths.

Use Scenario: Providing clean bias voltages to GaAs pHEMT amplifiers and quadrature modulators in 5G small-cell radios.

IC Role / Device Role / Timing Role: LDO2 delivers 5.0 V @ 300 mA with <60 µV_rms noise to PA bias rail; BUCK1 supplies 3.3 V to LO synthesizer IC.

Use Value: 50 mV dropout at full load extends PA operational time from single Li-ion cell (3.0 V min) without brownout.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail PMIC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADP5034ACPZ-1-R7	Factory-programmed fixed-output variant: BUCK1 = 3.3 V, BUCK2 = 1.8 V, LDO1 = 2.8 V, LDO2 = 1.2 V - no external feedback resistors required.	Suitable for production designs with unchanging rail requirements; eliminates resistor placement and layout tuning effort.	Select ADP5034ACPZ-1-R7 when rail voltages are finalized and board space is constrained - avoids external FB dividers.
TPS65023RSBR	TI device with 2× 600 mA bucks + 3× LDOs; lower max buck current (600 mA), no 3 MHz option (2.25 MHz max), different enable logic (active-low EN).	Used in legacy OMAP-based platforms; lacks ADP5034's 1200 mA capability and 3 MHz switching for ultra-compact designs.	Choose TPS65023RSBR only if migrating from existing TI-based designs - not recommended for new 3.3 V/1.2 V dual-core or FPGA projects needing >1 A buck current.

Compared with ADP5034ACPZ-1-R7, the -2-R7 offers full adjustability via FB pins for flexible rail tuning during prototyping; versus TPS65023RSBR, it delivers 2× higher buck current and 33% faster switching - critical for minimizing inductor size in portable RF modules.

Availability

ADP5034ACPZ-2-R7 is available at Aetrix Electronics and suitable for FPGA power management, portable medical instrumentation, and RF transceiver biasing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for ADP5034ACPZ-2-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP5034 belongs to Analog Devices' Power Management Unit (PMU) family designed specifically for space-constrained, multi-rail applications in portable computing, instrumentation, and communications equipment where efficiency, noise performance, and sequencing control are critical.

FAQ

What is the package type and thermal pad requirement for ADP5034ACPZ-2-R7?

The ADP5034ACPZ-2-R7 uses a 24-lead, 4 mm × 4 mm LFCSP package (CP-24-10) with an exposed thermal pad. Analog Devices explicitly recommends soldering the exposed pad directly to the PCB ground plane to achieve θ_JA = 35°C/W and ensure safe thermal operation at full 1200 mA buck load. Failure to connect the EPAD may cause junction temperature exceedance and premature shutdown.

Does ADP5034ACPZ-2-R7 support independent enable control for all four regulators?

Yes, ADP5034ACPZ-2-R7 provides four dedicated active-high enable pins: EN1 and EN2 for the buck regulators, EN3 and EN4 for the LDOs. Each pin accepts logic-high ≥1.1 V to activate its respective regulator, enabling precise power sequencing - for example, powering LDO1 first to stabilize analog references before enabling BUCK1 for digital core voltage.

What is the minimum input voltage required for the LDOs in ADP5034ACPZ-2-R7?

The LDO inputs (VIN3 and VIN4) of ADP5034ACPZ-2-R7 operate from 1.7 V to 5.5 V. However, minimum input depends on output voltage: VIN ≥ VOUT + 0.5 V is required for proper regulation. For instance, to deliver 3.3 V from LDO1, VIN3 must be ≥3.8 V; at 1.2 V output, VIN3 must be ≥1.7 V (the absolute minimum).

How does the MODE pin affect efficiency in ADP5034ACPZ-2-R7?

When MODE = low, ADP5034ACPZ-2-R7 enters auto PWM/PSM mode: above ~100 mA load, it operates in PWM for peak efficiency; below that threshold, it switches to power-save mode (PSM) to reduce quiescent current and maintain >85% efficiency at 1 mA. At MODE = high, forced PWM ensures constant 3 MHz operation - preferred for noise-sensitive systems needing deterministic frequency.

Can ADP5034ACPZ-2-R7 be used with ceramic output capacitors only?

Yes, ADP5034ACPZ-2-R7 is fully compatible with ceramic output capacitors. The datasheet specifies 10 µF minimum for buck outputs and 1 µF for LDO inputs/outputs, with ESR ≤1 Ω. X7R or X5R dielectrics are recommended; Y5V and Z5U types are explicitly discouraged due to poor DC bias and temperature stability - using them may cause instability or output droop under load.

ADP5034ACPZ-2-R7 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 24-WFQFN Exposed Pad, CSP

Packaging:: Tape & Reel (TR)

Product Status:: Active

Topology:: Step-Down (Buck) Synchronous (2), Linear (LDO) (2)

Number of Outputs:: 4

Frequency - Switching:: 3MHz

Voltage/Current - Output 1:: 0.8V ~ 3.8V, 1.2A

Voltage/Current - Output 2:: 0.8V ~ 3.8V, 1.2A

Voltage/Current - Output 3:: 0.8V ~ 4.75V, 300mA

w/LED Driver:: No

w/Supervisor:: No

w/Sequencer:: No

Voltage - Supply:: 1.7V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-LFCSP-WQ (4x4)

ADP5034ACPZ-2-R7 FAQ

1.How can I place an order for ADP5034ACPZ-2-R7 through Aetrix?

Please submit a Request for Quotation (RFQ) for ADP5034ACPZ-2-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADP5034ACPZ-2-R7 reliable?

The price and inventory of ADP5034ACPZ-2-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5034ACPZ-2-R7 is usually 5 days.

3.What payment methods are accepted for ADP5034ACPZ-2-R7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5034ACPZ-2-R7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADP5034ACPZ-2-R7?

ADP5034ACPZ-2-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADP5034ACPZ-2-R7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADP5034ACPZ-2-R7?

For technical support, including ADP5034ACPZ-2-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5034ACPZ-2-R7 requirements.

6.How does Aetrix verify that ADP5034ACPZ-2-R7 is sourced from the original manufacturer or authorized distributors?

All ADP5034ACPZ-2-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5034ACPZ-2-R7 meets industry standards.

7.What is the process for return or replacement of ADP5034ACPZ-2-R7?

All ADP5034ACPZ-2-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5034ACPZ-2-R7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADP5034ACPZ-2-R7 part is unused and in its original packaging.

Return procedure for ADP5034ACPZ-2-R7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…