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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear + Switching

Analog Devices Inc. ADP5037ACPZ-1-R7

Name: ADP5037ACPZ-1-R7
Brand: Analog Devices Inc.
SKU: ADP5037ACPZ-1-R7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADP5037ACPZ-1-R7

Manufacturer:: Analog Devices Inc.

Category:: Voltage Regulators - Linear + Switching

Package:: 24-WFQFN Exposed Pad, CSP

Datasheet:: ADP5037ACPZ-1-R7.pdf

Description:: IC REG QUAD BCK/LNR SYNC 24LFCSP

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Product details

Overview

ADP5037ACPZ-1-R7 from Analog Devices is a dual 3 MHz, 800 mA buck regulator with two 300 mA low-dropout (LDO) regulators in a single 24-lead 4 mm × 4 mm LFCSP package. It delivers precise, low-noise power to multiple voltage domains-supporting 0.8 V–3.8 V buck outputs and 0.8 V–5.2 V LDO outputs-with ±1.8% output accuracy, forced PWM/auto PSM mode selection via MODE pin, and out-of-phase buck operation to reduce input ripple. It is used in space-constrained portable instrumentation and FPGA/ASIC power sequencing.

For engineers reviewing the ADP5037ACPZ-1-R7 datasheet, ADP5037ACPZ-1-R7 pinout, ADP5037ACPZ-1-R7 application, or ADP5037ACPZ-1-R7 equivalent, key selection criteria include its dual-buck + dual-LDO integration, 3 MHz switching frequency enabling compact 1 µH inductors, high PSRR (>60 dB at 10 kHz) on LDOs, thermal shutdown at 150°C, and dedicated enable pins per channel for independent power rail control.

Technical Context

The ADP5037ACPZ-1-R7 integrates two synchronous buck regulators operating out of phase to minimize input capacitor requirements and improve EMI performance. Each buck supports 800 mA load with 2.5–3.5 MHz switching frequency, programmable via MODE pin for forced PWM or auto PWM/PSM operation-enabling high efficiency across light-to-heavy loads.

Its two LDOs feature low dropout (e.g., 75 mV at 3.3 V/300 mA), ultra-low output noise (60 µV rms for LDO2), and high PSRR (>60 dB up to 1 MHz), making them suitable for noise-sensitive analog and digital subsystems. All four regulators are independently enabled via dedicated EN pins and support factory-programmable or externally adjustable output voltages.

Key Specifications

Parameter	Value and Actual Design Meaning
Main input range	2.3 V to 5.5 V - powers both bucks and internal circuitry; compatible with single-cell Li-ion and 3.3 V/5 V rails.
Buck output current	800 mA per channel - sufficient for core logic or I/O rails of mid-performance FPGAs and processors.
LDO output current	300 mA per channel - supports analog sensors, RF bias, or low-power digital peripherals without external boost.
Switching frequency	3 MHz nominal - enables use of tiny 1 µH inductors and 10 µF ceramic output capacitors, reducing board area.
Output accuracy	±1.8% - ensures stable voltage margins for 1.2 V, 1.8 V, 2.8 V, and 3.3 V digital/analog supplies under line/load/temp variation.
LDO PSRR	>60 dB at 10 kHz - suppresses switching noise from adjacent bucks or noisy system rails feeding sensitive analog circuits.
Thermal shutdown	150°C with 20°C hysteresis - protects against sustained overload or poor PCB thermal design without requiring external monitoring.

Pinout & Package

ADP5037ACPZ-1-R7 uses a 24-lead, 4 mm × 4 mm LFCSP package with exposed pad (EPAD) recommended for soldering to AGND plane for thermal and electrical integrity.

Pin/Terminal	Circuit Role	Design Meaning
EN1, EN2, EN3, EN4	Independent enable inputs	Allow staggered startup, dynamic rail shutdown, and fault isolation-no shared control logic required.
MODE	Buck operating mode select	High = forced PWM (constant frequency); low = auto PWM/PSM (light-load efficiency optimization).
FB1–FB4	Feedback inputs	Support external resistor dividers for adjustable outputs or direct connection for fixed-voltage variants.
VIN1/VIN2, VIN3/VIN4	Dual input supplies	Enable independent sourcing: bucks from main rail (2.3–5.5 V), LDOs from lower/backup rail (1.7–5.5 V).
VOUT1–VOUT4	Output sensing nodes	Provide Kelvin sense points for accurate regulation-critical when PCB trace resistance affects load voltage.
SW1/SW2, PGND1/PGND2	Switching node & power ground	Dedicated paths minimize coupling between buck channels and simplify layout of high di/dt loops.

Key Features

Feature	Design Value
Out-of-phase buck operation	Reduces RMS input ripple by ~30%, allowing smaller input capacitors (≥4.7 µF) and easing EMI filtering.
Low-noise LDOs	60–100 µV_rms output noise (10 Hz–100 kHz) enables clean power for ADC references and RF synthesizers.
High PSRR LDOs	63 dB at 1 MHz for LDO1 - maintains signal integrity in mixed-signal SoCs where digital switching couples into analog supply.
Independent enable control	Four EN pins allow sequenced power-up/down, dynamic rail gating, and fault containment without external logic.
Thermal protection with hysteresis	150°C trip with 20°C hysteresis prevents thermal oscillation during transient overloads or airflow loss.

Applications

Portable Medical Sensors	FPGA Core & I/O Power
Use Scenario: Wearable ECG monitor with analog front-end, Bluetooth radio, and microcontroller. IC Role / Device Role / Timing Role: ADP5037ACPZ-1-R7 supplies 1.8 V (LDO1) to op-amps and ADC, 3.3 V (LDO2) to BLE radio, 1.2 V (BUCK1) to MCU core, and 2.5 V (BUCK2) to sensor interface. Use Value: Ultra-low LDO noise preserves ECG signal SNR; out-of-phase bucks minimize battery ripple; 4 mm × 4 mm footprint fits compact flex PCB.	Use Scenario: Low-power FPGA-based edge AI inference module with DDR3L memory and camera interface. IC Role / Device Role / Timing Role: ADP5037ACPZ-1-R7 delivers 1.0 V (BUCK1) to FPGA core, 1.8 V (BUCK2) to I/O bank, 3.3 V (LDO1) to camera sensor, and 1.2 V (LDO2) to DDR3L termination. Use Value: ±1.8% buck accuracy ensures FPGA timing closure; high PSRR LDOs prevent clock jitter from digital switching noise.
Space-Constrained Test Equipment	Multi-Rail Industrial Controller
Use Scenario: Handheld oscilloscope with 12-bit ADC, FPGA trigger engine, and LCD backlight driver. IC Role / Device Role / Timing Role: ADP5037ACPZ-1-R7 provides 3.3 V (LDO1) to ADC reference, 1.2 V (BUCK1) to FPGA fabric, 2.8 V (LDO2) to display driver, and 5.0 V (BUCK2 via external boost) - though BUCK2 max is 3.8 V, so this requires verification; instead: 1.8 V (BUCK2) to logic interface. Use Value: 3 MHz switching allows <10 mm² total passive area per buck; independent EN pins enable sleep-mode rail shutdown to extend battery life.	Use Scenario: DIN-rail PLC with isolated CAN, analog input conditioning, and ARM Cortex-M7 host. IC Role / Device Role / Timing Role: ADP5037ACPZ-1-R7 powers 3.3 V (LDO1) analog front-end, 1.2 V (BUCK1) Cortex-M7 core, 2.5 V (LDO2) isolated CAN transceiver, and 1.8 V (BUCK2) peripheral bus. Use Value: 150°C thermal shutdown protects against enclosure overheating; wide 1.7–5.5 V LDO input range accommodates aging 3.3 V backup rails.

Portable Medical Sensors

FPGA Core & I/O Power

Use Scenario: Wearable ECG monitor with analog front-end, Bluetooth radio, and microcontroller.

IC Role / Device Role / Timing Role: ADP5037ACPZ-1-R7 supplies 1.8 V (LDO1) to op-amps and ADC, 3.3 V (LDO2) to BLE radio, 1.2 V (BUCK1) to MCU core, and 2.5 V (BUCK2) to sensor interface.

Use Value: Ultra-low LDO noise preserves ECG signal SNR; out-of-phase bucks minimize battery ripple; 4 mm × 4 mm footprint fits compact flex PCB.

Use Scenario: Low-power FPGA-based edge AI inference module with DDR3L memory and camera interface.

IC Role / Device Role / Timing Role: ADP5037ACPZ-1-R7 delivers 1.0 V (BUCK1) to FPGA core, 1.8 V (BUCK2) to I/O bank, 3.3 V (LDO1) to camera sensor, and 1.2 V (LDO2) to DDR3L termination.

Use Value: ±1.8% buck accuracy ensures FPGA timing closure; high PSRR LDOs prevent clock jitter from digital switching noise.

Space-Constrained Test Equipment

Multi-Rail Industrial Controller

Use Scenario: Handheld oscilloscope with 12-bit ADC, FPGA trigger engine, and LCD backlight driver.

IC Role / Device Role / Timing Role: ADP5037ACPZ-1-R7 provides 3.3 V (LDO1) to ADC reference, 1.2 V (BUCK1) to FPGA fabric, 2.8 V (LDO2) to display driver, and 5.0 V (BUCK2 via external boost) - though BUCK2 max is 3.8 V, so this requires verification; instead: 1.8 V (BUCK2) to logic interface.

Use Value: 3 MHz switching allows <10 mm² total passive area per buck; independent EN pins enable sleep-mode rail shutdown to extend battery life.

Use Scenario: DIN-rail PLC with isolated CAN, analog input conditioning, and ARM Cortex-M7 host.

IC Role / Device Role / Timing Role: ADP5037ACPZ-1-R7 powers 3.3 V (LDO1) analog front-end, 1.2 V (BUCK1) Cortex-M7 core, 2.5 V (LDO2) isolated CAN transceiver, and 1.8 V (BUCK2) peripheral bus.

Use Value: 150°C thermal shutdown protects against enclosure overheating; wide 1.7–5.5 V LDO input range accommodates aging 3.3 V backup rails.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail PMIC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADP5034ACPZ-1-R7	Same 2-buck + 2-LDO architecture but supports 1.2 A buck current (vs. 800 mA); identical 24-lead LFCSP package.	Required where FPGA core or processor demands >800 mA at 1.0–1.2 V; higher current capability increases thermal load.	Select ADP5034ACPZ-1-R7 only if verified load exceeds 800 mA per buck; otherwise ADP5037ACPZ-1-R7 offers better light-load efficiency at lower cost.
TPS65023RGZR	TI part with 2× 600 mA bucks + 1× 300 mA LDO; different pinout, no MODE pin, fixed 2.25 MHz switching.	Lacks second LDO and independent MODE control; unsuitable for dual-noise-isolated analog/digital rails.	Choose only for cost-sensitive designs accepting reduced LDO count and fixed-frequency operation; not drop-in compatible.

Compared with ADP5034ACPZ-1-R7 and TPS65023RGZR, ADP5037ACPZ-1-R7 uniquely balances 800 mA buck capability with dual high-PSRR LDOs and selectable PWM/PSM mode-making it optimal for portable, noise-sensitive, space-constrained systems needing four independent regulated rails.

Availability

ADP5037ACPZ-1-R7 is available at Aetrix Electronics and suitable for portable medical devices, FPGA power management, and space-constrained test equipment requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant manufacturing.

Supply support for ADP5037ACPZ-1-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP5037ACPZ-1-R7 belongs to Analog Devices' Power Management Unit (PMU) family, designed specifically for compact, multi-rail power delivery in portable and instrumentation applications where efficiency, noise, and board area are critical constraints.

FAQ

What is the maximum output voltage supported by the buck regulators in ADP5037ACPZ-1-R7?

The buck regulators in ADP5037ACPZ-1-R7 support an output voltage range from 0.8 V to 3.8 V. This is confirmed in the General Description and Table 3 of the Rev. D datasheet. The upper limit of 3.8 V applies to both BUCK1 and BUCK2, regardless of input voltage within the 2.3 V–5.5 V range.

Does ADP5037ACPZ-1-R7 support independent power sequencing of its four outputs?

Yes, ADP5037ACPZ-1-R7 supports full independent sequencing via four dedicated enable pins (EN1–EN4). Each regulator can be turned on/off individually with no interdependency, enabling custom startup/shutdown order for FPGA, ASIC, or mixed-signal systems-verified in Pin Function Descriptions (Table 8) and Typical Application Circuit (Figure 1).

What is the typical output noise performance of the LDOs in ADP5037ACPZ-1-R7?

The LDOs in ADP5037ACPZ-1-R7 deliver 60 µV_rms (LDO2) and 100 µV_rms (LDO1) output noise over 10 Hz–100 kHz, measured at VOUT = 1.2 V and 2.8 V respectively with 5 V input. These values are specified in Table 4 and validated in Figures 39–40 of the Rev. D datasheet.

Can ADP5037ACPZ-1-R7 operate with a 2.3 V input supply across all regulators?

Yes, ADP5037ACPZ-1-R7 accepts 2.3 V–5.5 V on AVIN/VIN1/VIN2 (buck inputs) and 1.7 V–5.5 V on VIN3/VIN4 (LDO inputs). At 2.3 V input, BUCK1/BUCK2 remain functional down to 0.8 V output (per Table 3), while LDOs require headroom (e.g., ≥2.3 V input for 1.8 V LDO output), as defined in Table 4's dropout specifications.

What package type and thermal resistance does ADP5037ACPZ-1-R7 use?

ADP5037ACPZ-1-R7 uses a 24-lead, 4 mm × 4 mm LFCSP package with exposed pad. Its thermal resistance is θ_JA = 35°C/W and θ_JC = 3°C/W, specified in Table 7 of the Rev. D datasheet-enabling reliable operation up to +125°C junction temperature with proper PCB copper pour.

ADP5037ACPZ-1-R7 Specifications

Product attributes: Attribute value

Manufacturer:: Analog Devices Inc.

Series:: -

Package/Case:: 24-WFQFN Exposed Pad, CSP

Packaging:: Tape & Reel (TR)

Product Status:: Active

Topology:: Step-Down (Buck) Synchronous (2), Linear (LDO) (2)

Number of Outputs:: 4

Frequency - Switching:: 3MHz

Voltage/Current - Output 1:: 1.2V, 800mA

Voltage/Current - Output 2:: 3.3V, 800mA

Voltage/Current - Output 3:: 2.8V, 300mA

w/LED Driver:: No

w/Supervisor:: No

w/Sequencer:: No

Voltage - Supply:: 1.7V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-LFCSP-WQ (4x4)

ADP5037ACPZ-1-R7 FAQ

1.How can I place an order for ADP5037ACPZ-1-R7 through Aetrix?

Please submit a Request for Quotation (RFQ) for ADP5037ACPZ-1-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADP5037ACPZ-1-R7 reliable?

The price and inventory of ADP5037ACPZ-1-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5037ACPZ-1-R7 is usually 5 days.

3.What payment methods are accepted for ADP5037ACPZ-1-R7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5037ACPZ-1-R7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for ADP5037ACPZ-1-R7?

ADP5037ACPZ-1-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADP5037ACPZ-1-R7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADP5037ACPZ-1-R7?

For technical support, including ADP5037ACPZ-1-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5037ACPZ-1-R7 requirements.

6.How does Aetrix verify that ADP5037ACPZ-1-R7 is sourced from the original manufacturer or authorized distributors?

All ADP5037ACPZ-1-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5037ACPZ-1-R7 meets industry standards.

7.What is the process for return or replacement of ADP5037ACPZ-1-R7?

All ADP5037ACPZ-1-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5037ACPZ-1-R7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADP5037ACPZ-1-R7 part is unused and in its original packaging.

Return procedure for ADP5037ACPZ-1-R7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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