Analog Devices Inc. ADP5037ACPZ-2-R7

Overview

ADP5037ACPZ-2-R7 from Analog Devices is a quad-output power management IC integrating two 800 mA, 3 MHz synchronous buck regulators and two 300 mA low-dropout (LDO) regulators in a single 24-lead, 4 mm × 4 mm LFCSP package. It delivers precise, low-noise voltage regulation for multi-rail systems with tight board space constraints-e.g., powering FPGA core and I/O rails while supplying clean analog and digital domain voltages.

For engineers reviewing the ADP5037ACPZ-2-R7 datasheet, ADP5037ACPZ-2-R7 pinout, ADP5037ACPZ-2-R7 application, or ADP5037ACPZ-2-R7 equivalent, key selection criteria include its dual-buck out-of-phase switching architecture, ±1.8% output accuracy across temperature, factory-programmable or adjustable VOUT options, and high PSRR (>60 dB at 10 kHz) on both LDOs-critical for noise-sensitive RF and precision analog subsystems.

Technical Context

The ADP5037ACPZ-2-R7 implements independent enable control per regulator (EN1–EN4), dedicated MODE pin for forced PWM or auto PWM/PSM operation, and out-of-phase buck switching to reduce input capacitor RMS current. Its buck regulators feature 2.5–3.5 MHz switching frequency, 1200–1900 mA peak current limit, and integrated NMOS/PFET power stages with R_DS(ON) as low as 137 mΩ (PFET, 5.5 V).

LDO1 and LDO2 operate from 1.7 V to 5.5 V input, deliver up to 300 mA each, and maintain 50–180 mV dropout (depending on V_OUT and load), 60–64 dB PSRR up to 1 MHz, and <100 µV_RMS output noise (10 Hz–100 kHz). Feedback pins (FB1–FB4) support external resistor dividers for adjustable outputs or direct capacitor connection for fixed versions.

Key Specifications

Pinout & Package

ADP5037ACPZ-2-R7 uses a 24-lead, 4 mm × 4 mm LFCSP package with exposed thermal pad (EPAD) recommended to be soldered to AGND for optimal thermal performance and noise immunity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar quad-output PMIC applications.

Compared with ADP5034ACPZ-2-R7, the ADP5037ACPZ-2-R7 trades peak buck current for superior light-load PSM efficiency and lower system cost; versus TPS65023RSBR, it provides full quad-regulator integration and higher PSRR, eliminating need for external LDOs in noise-critical designs.

Availability

ADP5037ACPZ-2-R7 is available at Aetrix Electronics and suitable for FPGA power management, portable medical instrumentation, and space-constrained industrial IoT nodes requiring stable component supply, long-term lifecycle support, and guaranteed parametric compliance.

Supply support for ADP5037ACPZ-2-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.

The ADP5037ACPZ-2-R7 belongs to Analog Devices' Power Management Unit (PMU) family, designed specifically for compact, multi-rail power delivery in portable and embedded systems where board area, thermal density, and noise isolation are critical constraints.

FAQ

What is the maximum supported input voltage for the buck regulators in ADP5037ACPZ-2-R7?

The ADP5037ACPZ-2-R7 buck regulators (BUCK1 and BUCK2) accept an input voltage range of 2.3 V to 5.5 V on VIN1 and VIN2. Exceeding 5.5 V violates absolute maximum ratings and may cause permanent damage. The device also specifies UVLO thresholds (e.g., 3.9 V rising, 3.1 V falling) to ensure reliable startup under varying supply conditions.

Does ADP5037ACPZ-2-R7 support independent voltage sequencing between its four outputs?

Yes, ADP5037ACPZ-2-R7 supports full independent sequencing via four dedicated enable pins (EN1–EN4). Each regulator powers up only when its respective EN pin is driven high, allowing precise control over startup order-for example, enabling LDO1 before BUCK1 to pre-bias analog circuitry prior to digital core activation.

What is the typical output noise performance of the LDOs in ADP5037ACPZ-2-R7?

The ADP5037ACPZ-2-R7 LDOs deliver ≤100 µV_RMS output noise (10 Hz–100 kHz) - measured at 2.8 V output with 5 V input. LDO2 achieves 60 µV_RMS under same conditions. This low noise level is achieved through internal compensation and optimized pass transistor design, making ADP5037ACPZ-2-R7 suitable for powering precision ADCs and RF synthesizers.

Can ADP5037ACPZ-2-R7 operate in forced PWM mode across all load conditions?

Yes, ADP5037ACPZ-2-R7 enters forced PWM mode when the MODE pin is pulled high. In this mode, both buck regulators switch continuously at ~3 MHz regardless of load current, eliminating frequency variation and associated EMI spread - essential for systems requiring deterministic timing or EMI filtering at fixed frequencies.

What thermal resistance values apply to ADP5037ACPZ-2-R7 in its LFCSP package?

The ADP5037ACPZ-2-R7 in 24-lead LFCSP exhibits θ_JA = 35°C/W and θ_JC = 3°C/W when mounted on a standard JEDEC 2-layer board with the exposed pad soldered to a solid AGND plane. These values assume proper thermal land pattern per Analog Devices' layout guidelines - inadequate copper area increases junction temperature significantly.