Analog Devices Inc. ADP5070AREZ-R7

Overview

ADP5070AREZ-R7 from Analog Devices is a dual-output DC-to-DC switching regulator generating independently adjustable positive (up to +39 V) and negative (down to VIN − 39 V) rails from a single 2.85 V to 15 V input. It integrates a 1.0 A boost switch and 0.6 A inverting switch, supports 1.2 MHz/2.4 MHz operation or external synchronization (1.0–2.6 MHz), and delivers true shutdown with individual precision enable pins. It is used in bipolar analog signal chains requiring low-noise, symmetric ±15 V supplies for high-resolution ADCs and op-amps.

For engineers reviewing the ADP5070AREZ-R7 datasheet, ADP5070AREZ-R7 pinout, ADP5070AREZ-R7 application, or ADP5070AREZ-R7 equivalent, key selection criteria include independent output programming, out-of-phase switching for reduced input ripple, slew rate control for EMI mitigation, and thermal/overcurrent protection across −40°C to +125°C operation.

Technical Context

The ADP5070AREZ-R7 implements two independent PWM regulators: a boost stage with 1.0 A integrated MOSFET and an inverting stage with 0.6 A MOSFET, both operating at fixed frequency (1.2/2.4 MHz) or synchronized externally. Each regulator features separate error amplifiers (g_M = 270–330 μA/V), programmable soft start, and dedicated feedback inputs (FB1/FB2) referenced to AGND or VREF.

Start-up sequencing is configurable via SEQ pin (VPOS-first, VNEG-first, or simultaneous), while SLEW pin selects driver slew rate-open for fastest efficiency, VREG for normal, AGND for lowest EMI. Protection includes UVLO (2.85 V rising), OCP (1.1 A boost / 0.66 A inverter), OVP (0.86 V at FB1 / 0.74 V at FB2), and thermal shutdown (150°C).

Key Specifications

Pinout & Package

ADP5070AREZ-R7 is packaged in a 4 mm × 4 mm, 20-lead LFCSP with exposed pad (EPAD) that must be connected to AGND for thermal and electrical performance. The package supports high-power density layouts with low θ_JA = 60.2°C/W.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output DC-to-DC regulator applications.

Compared with ADP5070AREZ-R7, ADP5071AREZ-R7 offers higher output current headroom with identical footprint and sequencing logic, while MAX17504ATP+ demands external negative generation and lacks integrated soft-start coordination - making ADP5070AREZ-R7 optimal for compact, self-contained bipolar supply designs.

Availability

ADP5070AREZ-R7 is available at Aetrix Electronics and suitable for precision analog instrumentation, high-resolution data acquisition, and RF power amplifier biasing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for ADP5070AREZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.

The ADP5070 product line delivers dual-output, high-voltage DC-to-DC regulation for precision analog systems where independent, low-noise, and thermally robust power rails are essential - targeting test equipment, medical imaging, and optical communications.

FAQ

What is the maximum positive output voltage achievable with ADP5070AREZ-R7?

The ADP5070AREZ-R7 supports an adjustable positive output up to +39 V, determined by the internal 0.8 V feedback reference and external resistor divider on FB1. This is achievable across the full 2.85 V to 15 V input range, with verified operation at +34 V output in efficiency testing (Figure 12). The 39 V rating reflects the absolute maximum drain-source voltage of the integrated boost switch.

Can ADP5070AREZ-R7 generate a negative output lower than −15 V?

Yes, ADP5070AREZ-R7 can generate negative outputs down to VIN − 39 V. For example, with a 5 V input, it delivers stable −34 V (Figure 15), and with 12 V input, −27 V is attainable. The inverter stage uses a 1.6 V internal reference and FB2 feedback, enabling precise programming across this full range with ±1.5% accuracy over −40°C to +125°C.

How does the SEQ pin affect startup behavior in ADP5070AREZ-R7?

The SEQ pin configures the ADP5070AREZ-R7's startup sequence: open = manual EN control; tied to VREG = simultaneous VPOS/VNEG ramp; pulled low = sequenced startup where either EN1 or EN2 determines first-rail activation. This prevents reverse biasing of op-amps or ADC inputs during power-up and is validated in Figures 29–33 transient waveforms.

Is ADP5070AREZ-R7 compatible with external clock synchronization?

Yes, ADP5070AREZ-R7 accepts an external clock signal on the SYNC/FREQ pin across 1.0 MHz to 2.6 MHz. The device locks its internal oscillator to the external source, enabling EMI reduction through frequency alignment with system clocks - confirmed in Figures 24 and 27 showing stable synchronization across temperature and input voltage.

What thermal performance can be expected from ADP5070AREZ-R7 in a standard 4-layer PCB layout?

On a 4-layer PCB with nine thermal vias connecting the exposed pad to AGND, ADP5070AREZ-R7 achieves θ_JA = 60.2°C/W (LFCSP). At full load (1.0 A boost + 0.6 A inverter), junction temperature rise is ~60°C above ambient - well within the −40°C to +125°C rating. Layout guidelines in the datasheet (Page 26) confirm this performance is repeatable with recommended copper pour and via patterns.