Analog Devices Inc. ADP5071ACPZ
- Part No.:
- ADP5071ACPZ
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADP5071ACPZ.pdf
- Description:
- IC REG BST SEPIC ADJ DL 20LFCSP
- Quantity:
- Payment:

- Shipping:

Inventory:861
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Product details
Overview
ADP5071 from Analog Devices is a dual high-performance DC-to-DC switching regulator generating independently regulated +39 V positive and −39 V negative outputs from a 2.85 V to 15 V input. It integrates a 2.0 A boost switch and 1.2 A inverting switch, supports 1.2 MHz/2.4 MHz switching (with external sync up to 2.6 MHz), and delivers symmetric or sequenced startup for bipolar supply rails in precision analog systems.
For engineers reviewing the ADP5071 datasheet, ADP5071 pinout, ADP5071 application, or ADP5071 equivalent, key selection criteria include independent resistor-programmable VPOS/VNEG outputs, true shutdown with <10 µA quiescent current in shutdown, out-of-phase operation for reduced input ripple, slew rate control for EMI mitigation, and thermal/overcurrent/overvoltage protection across −40°C to +125°C junction temperature.
Technical Context
The ADP5071 implements two independent PWM-controlled regulators: a boost stage with 0.8 V feedback reference and 175 mΩ RDS(ON), and an inverting stage with 1.6 V internal reference and 350 mΩ RDS(ON). Both use current-mode control with transconductance error amplifiers (gm = 270–330 µA/V) and programmable soft start (4–32 ms).
It features precision enable inputs (EN1/EN2) with 1.05 V threshold and 1.48 MΩ internal pull-down, SEQ pin for manual/simultaneous/sequenced startup, and SLEW pin to select fast/normal/slow driver slew rates-directly impacting efficiency vs. noise trade-offs in sensitive RF and data acquisition designs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.85 V to 15 V - supports single-cell Li-ion, USB, and industrial 5 V/12 V rails without pre-regulation. |
| Positive Output Range | Up to +39 V - adjustable via FB1 resistor divider; enables high-voltage op-amp bias and CCD applications. |
| Negative Output Range | Down to VIN − 39 V - e.g., −34 V at 5 V input; supports rail-to-rail analog signal conditioning with true bipolar supplies. |
| Switching Frequency | 1.2 MHz or 2.4 MHz (pin-selectable); externally synchronizable from 1.0 MHz to 2.6 MHz for EMI-sensitive systems. |
| Current Limits | Boost: 2.0–2.4 A; Inverter: 1.2–1.44 A - defines maximum continuous output current under thermal limits. |
| Quiescent Current | 4.0 mA typical operating; 10 µA max shutdown - critical for battery-powered portable instrumentation. |
| Protection Features | UVLO (2.85 V rising), OCP, OVP (at FB pins), TSD (150°C), and true load disconnect in shutdown mode. |
Pinout & Package
ADP5071 is available in two thermally enhanced packages: 4 mm × 4 mm, 20-lead LFCSP (exposed pad) and 20-lead TSSOP (exposed pad), both rated for −40°C to +125°C junction temperature. The exposed pad must be connected to AGND for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1 | Boost Regulator Precision Enable | Enables VPOS only when voltage exceeds 1.05 V threshold; allows independent control of positive rail startup. |
| EN2 | Inverting Regulator Precision Enable | Enables VNEG only when voltage exceeds 1.05 V threshold; enables asymmetric sequencing (e.g., VNEG first). |
| SEQ | Startup Sequence Control | Open = manual EN1/EN2 control; tied to VREG = simultaneous startup; grounded = sequenced (VPOS or VNEG first). |
| SYNC/FREQ | Oscillator Mode Selection & Sync Input | Low = 1.2 MHz; high = 2.4 MHz; driven by external clock = synchronization from 1.0–2.6 MHz for noise reduction. |
| SLEW | Driver Slew Rate Control | Open = fastest slew (best efficiency); VREG = normal; AGND = slowest (lowest EMI, optimal for RF/ADC systems). |
| FB1 / FB2 | Feedback Inputs | FB1 sets VPOS via resistor divider to 0.8 V reference; FB2 sets VNEG via divider to VREF − 0.8 V (1.6 V − 0.8 V = 0.8 V). |
| VREF | Inverting Regulator Reference Output | 1.6 V precision reference; requires 1.0 µF ceramic capacitor to AGND for stable inverter regulation. |
| VREG | Internal Regulator Output | 4.25 V supply for internal circuitry and external bias; requires 1.0 µF ceramic capacitor to AGND. |
| SW1 / SW2 | Switching Nodes | SW1 connects to boost inductor/diode; SW2 connects to inverter inductor/diode; both swing beyond rail limits (±40 V). |
| PGND / AGND | Power & Analog Grounds | Separate ground pins minimize noise coupling; exposed pad must connect to AGND for thermal path and reference stability. |
Key Features
| Feature | Design Value |
|---|---|
| Independent Output Programming | VPOS and VNEG set separately via FB1/FB2 resistor dividers - enables asymmetric ±15 V, ±12 V, or custom rails without external DACs. |
| Out-of-Phase Switching | SW1 and SW2 driven 180° apart - reduces input capacitor RMS current and input supply ripple by ~30% versus in-phase operation. |
| Programmable Soft Start | 4 ms (SS open) to 32 ms (50 kΩ to GND) - prevents inrush current into large output capacitors during power-up. |
| Slew Rate Control | Three discrete driver slew settings via SLEW pin - balances switching loss (efficiency) against conducted EMI in mixed-signal PCBs. |
| True Shutdown | Both regulators fully disconnect loads from PVIN; ISHDN ≤ 10 µA - essential for zero-power standby in portable medical devices. |
Applications
| Bipolar Amplifier Supply | CCD Bias Supply |
|---|---|
|
Use Scenario: Powering high-precision op-amps and instrumentation amplifiers requiring low-noise, matched ±15 V rails. IC Role / Device Role / Timing Role: Dual-regulator IC generating independent, tightly regulated positive and negative outputs with <±1.5% feedback accuracy over temperature. Use Value: Eliminates need for discrete charge-pump or transformer-based bipolar supplies; reduces board area by >40% and improves PSRR by enabling local regulation near analog ICs. |
Use Scenario: Providing high-voltage, low-ripple bias for scientific-grade CCD image sensors in spectroscopy and astronomy equipment. IC Role / Device Role / Timing Role: Generates up to +39 V VPOS and −34 V VNEG from 5 V input, with programmable soft start to prevent sensor damage during power-up. Use Value: Replaces multi-stage DC/DC + linear post-regulators; achieves <10 mVpp output ripple at 1.2 MHz switching, meeting CCD dark-current specifications. |
| Optical Module Supply | RF Power Amplifier Bias |
|
Use Scenario: Delivering isolated ±5 V to ±12 V rails for laser diode drivers and transimpedance amplifiers in fiber-optic transceivers. IC Role / Device Role / Timing Role: Provides symmetric startup (SEQ = VREG) and synchronized switching to minimize crosstalk between analog and digital sections of optical modules. Use Value: Enables compact SFP+ and QSFP module designs; out-of-phase operation cuts input capacitor size by 50% versus single-rail converters. |
Use Scenario: Supplying gate and drain bias voltages to GaAs/GaN RF PAs in 5G base station front-ends and test equipment. IC Role / Device Role / Timing Role: Delivers stable +28 V VPOS and −5 V VNEG with fast transient response (<15 µs recovery) and hiccup-mode OCP for fault containment. Use Value: Supports Class AB PA operation without external LDOs; slew rate control minimizes switching noise injection into RF signal paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DC-DC regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5070 | Lower current capability: 1.0 A boost / 0.6 A inverter; same pinout and feature set. | Not suitable for >1 A VPOS or >600 mA VNEG loads; limited to lower-power ADC/DAC biasing. | Select ADP5070 only when output current requirements are ≤1 A positive / ≤600 mA negative and cost optimization is prioritized. |
| LT3582 | Single 2 MHz buck-boost regulator with integrated FETs; generates only one output (positive or negative), not both simultaneously. | Requires two separate ICs to replicate ADP5071's dual-rail functionality; lacks independent sequencing and out-of-phase operation. | Choose LT3582 only for space-constrained single-rail designs where dual-output integration is unnecessary and layout simplicity outweighs efficiency loss. |
Compared with ADP5070 and LT3582, the ADP5071 uniquely integrates matched 2.0 A/1.2 A switches, independent feedback loops, and hardware-controlled sequencing in one package-enabling compact, high-efficiency bipolar supply generation without compromising on transient response or protection robustness.
Availability
ADP5071 is available at Aetrix Electronics and suitable for precision analog instrumentation, optical transceiver modules, RF power amplifier biasing, and portable medical imaging systems requiring stable component supply across extended temperature ranges.
Supply support for ADP5071 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets since 1965.
The ADP5071 belongs to Analog Devices' precision power management product line, designed specifically for applications demanding clean, independently regulated bipolar supplies with minimal board footprint and full system-level protection.
FAQ
What input voltage range does the ADP5071 support?
The ADP5071 supports an input voltage range of 2.85 V to 15 V across PVIN1, PVIN2, and PVINSYS pins. This range accommodates single-cell Li-ion batteries (2.85–4.2 V), USB 5 V, and industrial 12 V rails. Operation below 2.85 V triggers UVLO shutdown; exceeding 15 V risks absolute maximum rating violation.
How do I set independent positive and negative output voltages on the ADP5071?
Set VPOS using a resistor divider from VPOS to AGND connected to FB1 (0.8 V reference); set VNEG using a divider from VNEG to VREF (1.6 V) connected to FB2 (0.8 V reference relative to VREF). The ADP5071 datasheet provides exact formulas and example values for common outputs like ±12 V and ±15 V.
Does the ADP5071 support synchronized switching with an external clock?
Yes, the ADP5071 supports external synchronization via the SYNC/FREQ pin, accepting clock signals from 1.0 MHz to 2.6 MHz. When driven by an external source, the internal oscillator locks to the input frequency, enabling noise-sensitive systems (e.g., high-speed ADCs) to align switching edges outside critical frequency bands.
What is the purpose of the SEQ pin on the ADP5071?
The SEQ pin configures startup behavior: open for manual EN1/EN2 control; tied to VREG for simultaneous VPOS/VNEG startup; grounded for sequenced startup (VPOS first if EN1 rises first, or VNEG first if EN2 rises first). This eliminates external timing circuitry for complex power sequencing in FPGA or DSP systems.
Can the ADP5071 operate in SEPIC configuration?
Yes, the ADP5071's boost regulator supports optional SEPIC operation using the INBK pin, enabling automatic step-up/step-down functionality when input voltage may fall above or below the desired VPOS. This requires specific external component selection per the ADP5071 datasheet's SEPIC section and is not enabled by default.
ADP5071ACPZ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad, CSP
- Packaging:
- Tray
- Product Status:
- Active
- Function:
- Step-Up, Step-Up/Step-Down
- Output Configuration:
- Positive and Negative (Dual Rail)
- Topology:
- Boost, SEPIC
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.85V
- Voltage - Input (Max):
- 15V
- Voltage - Output (Min/Fixed):
- 0.8V, 1.6V
- Voltage - Output (Max):
- ±39V
- Current - Output:
- 1.2A, 2A
- Frequency - Switching:
- 1.2MHz, 2.4MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-LFCSP (4x4)
ADP5071ACPZ FAQ
1.How can I place an order for ADP5071ACPZ through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5071ACPZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5071ACPZ reliable?
The price and inventory of ADP5071ACPZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5071ACPZ is usually 5 days.
3.What payment methods are accepted for ADP5071ACPZ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5071ACPZ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5071ACPZ?
ADP5071ACPZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5071ACPZ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5071ACPZ?
For technical support, including ADP5071ACPZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5071ACPZ requirements.
6.How does Aetrix verify that ADP5071ACPZ is sourced from the original manufacturer or authorized distributors?
All ADP5071ACPZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5071ACPZ meets industry standards.
7.What is the process for return or replacement of ADP5071ACPZ?
All ADP5071ACPZ units undergo pre-shipment inspection (PSI). If there is an issue with ADP5071ACPZ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5071ACPZ part is unused and in its original packaging.
Return procedure for ADP5071ACPZ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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