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Analog Devices Inc. ADP5071ACPZ-R7
- Part No.:
- ADP5071ACPZ-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADP5071ACPZ-R7.pdf
- Description:
- IC REG BST SEPIC ADJ DL 20LFCSP
- Quantity:
- Payment:
- Shipping:
Inventory:3,197
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Product details
Overview
ADP5071ACPZ-R7 from Analog Devices is a dual-output DC-DC switching regulator integrating independent boost and inverting regulators to generate programmable positive (up to +39 V) and negative (down to VIN − 39 V) rails from a single 2.85 V to 15 V input. It delivers 2.0 A peak current on the boost channel and 1.2 A on the inverting channel, with 1.2 MHz/2.4 MHz selectable switching frequency and true shutdown for both outputs - used in bipolar supply generation for precision analog signal chains.
For engineers reviewing the ADP5071ACPZ-R7 datasheet, ADP5071ACPZ-R7 pinout, ADP5071ACPZ-R7 application, or ADP5071ACPZ-R7 equivalent, key selection criteria include independent output regulation, slew rate control for EMI reduction, resistor-programmable soft start, out-of-phase operation, and thermal/overcurrent/overvoltage protection across −40°C to +125°C junction temperature.
Technical Context
The ADP5071ACPZ-R7 implements two independent PWM-controlled switching regulators: a boost stage with integrated 2.0 A MOSFET (RDS(ON) = 175 mΩ, VDS(MAX) = 39 V) and an inverting stage with integrated 1.2 A MOSFET (RDS(ON) = 350 mΩ, VDS(MAX) = 39 V). Both use current-mode control with transconductance error amplifiers (gM = 270–330 µA/V) and support external compensation via COMP1/COMP2 pins.
It features synchronized 180° out-of-phase switching, programmable slew rate (via SLEW pin), flexible sequencing (VPOS-first, VNEG-first, or simultaneous), and full protection suite including UVLO (2.85 V rising threshold), OCP (2.2 A typical boost / 1.32 A typical inverter), OVP (0.86 V at FB1, 0.74 V at FB2), and thermal shutdown (150°C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.85 V to 15 V - supports wide-input industrial, optical, and RF bias applications without pre-regulation. |
| Positive Output Range | Up to +39 V - adjustable via FB1 resistor divider; enables high-voltage op-amp and CCD bias supplies. |
| Negative Output Range | Down to VIN − 39 V - enables deep negative rails (e.g., −34 V at VIN = 5 V) for RF PA bias and DAC reference. |
| Switching Frequency | 1.2 MHz or 2.4 MHz (pin-selectable); externally synchronizable from 1.0 MHz to 2.6 MHz - simplifies EMI filtering in noise-sensitive systems. |
| Quiescent Current | 4.0 mA typical (operating), 10 µA max (shutdown) - minimizes standby power in battery-backed instrumentation. |
| Protection Features | UVLO, OCP, OVP, TSD - ensures robust operation under fault conditions without external supervision circuitry. |
| Junction Temperature | −40°C to +125°C - qualified for automotive under-hood and industrial control environments. |
Pinout & Package
ADP5071ACPZ-R7 is packaged in a 4 mm × 4 mm, 20-lead LFCSP (Lead Frame Chip Scale Package) with exposed pad connected to AGND. This thermally enhanced package supports high-power density layouts and meets JEDEC J-STD-020 reflow requirements.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW1 | Boost Regulator Switch Node | Connects to inductor/diode node of boost converter; requires low-inductance layout to minimize EMI and voltage spikes. |
| SW2 | Inverting Regulator Switch Node | Connects to inductor/diode node of inverting converter; operates 180° out-of-phase with SW1 to reduce input ripple. |
| FB1 | Boost Output Feedback Input | Resistor divider from VPOS to AGND sets regulated positive output; 0.8 V reference enables precise voltage programming. |
| FB2 | Inverting Output Feedback Input | Resistor divider from VNEG to VREF sets regulated negative output; uses 0.8 V reference relative to VREF (1.6 V). |
| EN1 / EN2 | Precision Enable Inputs | Independent logic-controlled enables with 1.15 V threshold; allow asymmetric startup sequencing or individual rail disable. |
| SEQ | Startup Sequence Control | Selects VPOS-first, VNEG-first, or simultaneous startup by tying to VREG, AGND, or left open - critical for analog system reliability. |
| SLEW | Driver Slew Rate Control | Configures fast (open), normal (to VREG), or slow (to AGND) MOSFET gate drive - trade-off between efficiency and EMI performance. |
| SS | Soft Start Timer Input | Resistor-to-AGND programs soft start time from 4 ms (open) to 32 ms - prevents inrush current into large output capacitors. |
| SYNC/FREQ | Frequency Selection & Sync Input | Logic level selects 1.2 MHz (low) or 2.4 MHz (high); accepts external clock 1.0–2.6 MHz for system-level noise coordination. |
| PGND / AGND | Power & Analog Ground | Separate ground pins require star-point connection at exposed pad; minimizes noise coupling between switching and sensitive analog circuits. |
Key Features
| Feature | Design Value |
|---|---|
| Independent Positive/Negative Regulation | Each output programmable via dedicated feedback resistors (FB1/FB2), enabling asymmetric ±15 V, ±12 V, or custom rails without cross-coupling. |
| Out-of-Phase Switching | SW1 and SW2 driven 180° apart reduces input capacitor RMS current and lowers conducted EMI at fundamental frequency. |
| Programmable Slew Rate | Three-step driver slew control (via SLEW pin) allows optimization of switching loss vs. radiated emissions in final PCB layout. |
| Flexible Startup Sequencing | SEQ pin configures manual enable, simultaneous, VPOS-first, or VNEG-first startup - prevents latch-up in op-amp and ADC front-ends. |
| True Shutdown Mode | Both regulators fully disconnect loads from input when EN1/EN2 are low; shutdown current ≤10 µA eliminates leakage paths. |
| Integrated Protection Suite | UVLO, cycle-by-cycle OCP, output OVP, and thermal shutdown operate autonomously - no external monitoring IC required. |
Applications
| Bipolar Amplifier Supply | CCD Bias Generation |
|---|---|
|
Use Scenario: Powering high-precision operational amplifiers requiring symmetric ±15 V rails with tight regulation and low noise. IC Role / Device Role / Timing Role: Dual-rail DC-DC regulator generating independently regulated VPOS and VNEG outputs with <±1.5% feedback accuracy over temperature. Use Value: Eliminates need for discrete boost + inverter ICs or transformer-based supplies; achieves <10 mV p-p output ripple with proper layout and filtering. |
Use Scenario: Providing high-voltage negative bias (e.g., −24 V to −34 V) for charge-coupled device image sensors in scientific cameras. IC Role / Device Role / Timing Role: Inverting regulator delivering up to 1.2 A at VIN − 39 V with programmable soft start to prevent sensor damage during power-up. Use Value: Enables single-supply input (5 V or 12 V) to generate deep negative bias without external high-voltage DC-DC stages or transformers. |
| Optical Module Bias | RF Power Amplifier Bias |
|
Use Scenario: Supplying bias voltages for laser diode drivers and transimpedance amplifiers in fiber-optic transceivers. IC Role / Device Role / Timing Role: Generates stable +5 V and −5.2 V rails with out-of-phase switching to minimize supply-induced jitter on high-speed data lanes. Use Value: Reduces input ripple by >40% compared to in-phase dual converters, improving signal integrity in 25+ Gbps optical links. |
Use Scenario: Delivering adjustable positive (e.g., +10 V) and negative (e.g., −5 V) bias to GaAs/GaN RF power amplifier stages in wireless infrastructure. IC Role / Device Role / Timing Role: Dual-channel regulator supporting dynamic envelope tracking with fast load transient response (<15 µs recovery) and hiccup-mode OCP. Use Value: Maintains stable bias under pulsed RF load conditions; thermal shutdown prevents damage during antenna mismatch events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DC-DC regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5070ACPZ-R7 | Lower current capability: 1.0 A boost / 0.6 A inverter; identical pinout and feature set. | Suitable for lower-power analog systems where 2 A/1.2 A headroom is unnecessary. | Select ADP5070ACPZ-R7 only if load currents remain below 800 mA on either rail to ensure margin and thermal safety. |
| LT3582EFE#TRPBF | Single-chip dual-output regulator with 1.3 A boost / 0.8 A inverter; different pinout, no SEQ/SLEW pins, fixed 1.2 MHz frequency. | Lacks programmable sequencing and slew control; simpler interface but less flexible for noise-critical designs. | Choose LT3582EFE#TRPBF when board space is constrained and advanced sequencing/EMI control is not required. |
Compared with ADP5071ACPZ-R7, ADP5070ACPZ-R7 offers identical functionality at reduced current rating, while LT3582EFE#TRPBF provides a compact alternative with fewer configuration options but no external frequency sync or slew adjustment - making ADP5071ACPZ-R7 optimal for high-performance, noise-sensitive, and thermally demanding bipolar supply designs.
Availability
ADP5071ACPZ-R7 is available at Aetrix Electronics and suitable for optical module supply, RF power amplifier bias, and precision ADC/DAC reference applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for ADP5071ACPZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with design centers worldwide and a focus on precision, power, and reliability.
The ADP5071 belongs to Analog Devices' high-efficiency, dual-output DC-DC regulator product line, designed specifically for applications needing independent, well-regulated positive and negative supplies from a single input - such as test equipment, medical imaging, and communications infrastructure.
FAQ
What is the maximum positive output voltage achievable with the ADP5071ACPZ-R7?
The ADP5071ACPZ-R7 supports an adjustable positive output voltage up to +39 V, limited by the 39 V maximum drain-source voltage rating of its integrated boost switch. This is achieved using a resistor divider from VPOS to AGND connected to the FB1 pin, which references a precise 0.8 V internal bandgap. Operation above 39 V risks permanent damage to the internal MOSFET.
Can the ADP5071ACPZ-R7 generate a negative output more negative than −39 V?
No. The ADP5071ACPZ-R7's inverting regulator supports a negative output down to VIN − 39 V - meaning its most negative output is constrained by both input voltage and the 39 V VDS(MAX) rating of the inverter switch. For example, with VIN = 5 V, the deepest achievable VNEG is −34 V; with VIN = 12 V, it is −27 V. Exceeding this violates absolute maximum ratings.
How does the SEQ pin affect startup behavior of the ADP5071ACPZ-R7?
The SEQ pin on the ADP5071ACPZ-R7 determines startup sequence: open for manual enable (EN1/EN2 control each rail independently), tied to VREG for simultaneous startup (both rails enabled together when EN2 rises), or pulled low for sequenced startup (EN1 or EN2 selects first rail). This prevents latch-up in op-amps and ADCs by ensuring proper power-up order.
Does the ADP5071ACPZ-R7 support external synchronization of its switching frequency?
Yes. The ADP5071ACPZ-R7 accepts an external clock signal on the SYNC/FREQ pin across 1.0 MHz to 2.6 MHz. When driven by a clean CMOS clock, the internal PLL locks to the external source - enabling noise-sensitive applications (e.g., high-speed ADCs or RF receivers) to align switching harmonics away from critical frequency bands.
What is the purpose of the SLEW pin on the ADP5071ACPZ-R7?
The SLEW pin on the ADP5071ACPZ-R7 configures the gate driver slew rate for both SW1 and SW2 nodes: open for fastest slew (best efficiency), tied to VREG for medium slew (balanced performance), or tied to AGND for slowest slew (lowest EMI). This direct hardware control allows layout-specific EMI tuning without changing compensation or frequency.
ADP5071ACPZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Up, Step-Up/Step-Down
- Output Configuration:
- Positive and Negative (Dual Rail)
- Topology:
- Boost, SEPIC
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.85V
- Voltage - Input (Max):
- 15V
- Voltage - Output (Min/Fixed):
- 0.8V, 1.6V
- Voltage - Output (Max):
- ±39V
- Current - Output:
- 1.2A, 2A
- Frequency - Switching:
- 1.2MHz, 2.4MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-LFCSP (4x4)
ADP5071ACPZ-R7 FAQ
1.How can I place an order for ADP5071ACPZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5071ACPZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5071ACPZ-R7 reliable?
The price and inventory of ADP5071ACPZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5071ACPZ-R7 is usually 5 days.
3.What payment methods are accepted for ADP5071ACPZ-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5071ACPZ-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5071ACPZ-R7?
ADP5071ACPZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5071ACPZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5071ACPZ-R7?
For technical support, including ADP5071ACPZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5071ACPZ-R7 requirements.
6.How does Aetrix verify that ADP5071ACPZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5071ACPZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5071ACPZ-R7 meets industry standards.
7.What is the process for return or replacement of ADP5071ACPZ-R7?
All ADP5071ACPZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5071ACPZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5071ACPZ-R7 part is unused and in its original packaging.
Return procedure for ADP5071ACPZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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