Analog Devices Inc. ADP5072ACBZ-R7
- Part No.:
- ADP5072ACBZ-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-UFBGA, WLCSP
- Datasheet:
-
ADP5072ACBZ-R7.pdf
- Description:
- IC REG BOOST ADJ DL 20WLCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP5072ACBZ-R7 from Analog Devices is a dual-output, high-efficiency DC-DC switching regulator generating independently adjustable positive (up to +35 V) and negative (down to −30 V) rails from a 2.85 V to 5.5 V input. It integrates a 1.0 A boost switch and 0.6 A inverting switch, operates at 1.2 MHz or 2.4 MHz (synchronizable), and supports precision sequencing for bipolar supply systems in precision analog signal chains.
For engineers reviewing the ADP5072ACBZ-R7 datasheet, ADP5072ACBZ-R7 pinout, ADP5072ACBZ-R7 application, or ADP5072ACBZ-R7 equivalent, key selection criteria include independent output regulation, slew rate control for EMI reduction, resistor-programmable soft start, out-of-phase switching, and WLCSP package suitability for space-constrained PCB layouts.
Technical Context
The ADP5072ACBZ-R7 implements two independent PWM-controlled regulators: a boost stage with 1.0 A integrated MOSFET and an inverting stage with 0.6 A integrated MOSFET. Both use current-mode control with transconductance error amplifiers (gM = 260–340 µA/V) and feature programmable minimum on/off times (50/25 ns boost; 60/50 ns inverter).
It employs a PLL-based oscillator supporting pin-selectable 1.2 MHz/2.4 MHz operation or external synchronization from 1.0 MHz to 2.6 MHz. Slew rate control on SW1/SW2 drivers is configured via the SLEW pin (open/AVIN/AGND), and start-up sequencing (VPOS-first, VNEG-first, or simultaneous) is managed by the SEQ pin with individual EN1/EN2 enables referenced to internal 1.15 V thresholds.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input voltage range | 2.85 V to 5.5 V - supports single-cell Li-ion, USB, or regulated 3.3 V/5 V rails without pre-regulation. |
| Positive output range | Up to +35 V - enables high-voltage bias for CCDs, RF PAs, and TOF sensors using external resistive feedback. |
| Negative output range | Down to −30 V - provides symmetric dual-rail support for op-amps, ADCs, DACs, and multiplexers. |
| Switching frequency | 1.2 MHz or 2.4 MHz (pin-selectable); synchronizable 1.0–2.6 MHz - allows noise-sensitive system-level clock alignment. |
| Soft start time | 4 ms (SS open) to 32 ms (SS = 50 kΩ to AGND) - prevents inrush current and stabilizes reference startup before regulation. |
| Thermal shutdown | 150°C threshold with 15°C hysteresis - protects against sustained overload or poor PCB thermal design. |
| Quiescent current | 4.0 mA typical (both regulators active); 2.2 mA standby - minimizes power loss in always-on subsystems. |
Pinout & Package
The ADP5072ACBZ-R7 is housed in a 1.61 mm × 2.18 mm, 20-ball WLCSP (Wafer-Level Chip Scale Package) with 0.4 mm pitch, rated for −40°C to +125°C junction temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVIN, AVIN | Power inputs | PVIN supplies inverter switch; AVIN powers internal circuitry and boost switch - separate paths reduce coupling noise. |
| SW1, SW2 | Switching nodes | SW1 drives boost inductor; SW2 drives inverting inductor - driven 180° out of phase to minimize input ripple current. |
| EN1, EN2 | Precision enable inputs | Enable boost/inverter independently with 1.15 V threshold - supports flexible power sequencing without external logic. |
| FB1, FB2 | Feedback inputs | FB1 sets VPOS via resistor divider to AGND; FB2 sets VNEG via divider to VREF - enables independent output programming. |
| SLEW, SEQ, SS | Control configuration pins | SLEW configures driver slew rate; SEQ selects startup mode; SS programs soft start duration - all resistor-configurable, no external ICs needed. |
Key Features
| Feature | Design Value |
|---|---|
| Independent output regulation | Separate feedback loops (FB1/FB2) and error amplifiers allow simultaneous but uncorrelated VPOS and VNEG adjustment without cross-regulation impact. |
| Out-of-phase switching | SW1 and SW2 driven 180° apart reduces peak input current demand and lowers RMS input capacitor ripple current by ~30%. |
| Slew rate control | Three SLEW pin states (open/AVIN/AGND) adjust gate drive speed - trade-off between efficiency (fast) and EMI/noise (slow) without changing layout. |
| Flexible start-up sequencing | SEQ pin configures manual, simultaneous, VPOS-first, or VNEG-first startup - eliminates need for external sequencers in dual-rail analog systems. |
| Resistor-programmable soft start | SS pin accepts external resistor to AGND (0–50 kΩ) to scale soft start time from 4 ms to 32 ms - prevents overshoot during power-up across wide load ranges. |
Applications
| Bipolar Amplifier Supply | CCD Bias Supply |
|---|---|
Use Scenario: Powering high-precision instrumentation op-amps requiring low-noise ±15 V rails with tight regulation and minimal cross-talk. IC Role / Device Role / Timing Role: Dual-rail DC-DC converter generating isolated, independently trimmed positive and negative outputs with out-of-phase switching to suppress supply-induced distortion. Use Value: Achieves <±1.5% output accuracy over −40°C to +125°C and <0.002%/V line regulation - critical for 16-bit+ data acquisition systems. | Use Scenario: Providing programmable high-voltage bias (e.g., +24 V to +35 V) for charge-coupled device image sensors in medical or industrial cameras. IC Role / Device Role / Timing Role: Boost regulator delivering stable, adjustable high-voltage rail with soft-start control to prevent sensor damage during power-up. Use Value: Supports up to +35 V output with 0.8 V feedback reference and <0.5% typical accuracy - enables precise pixel charge control and dark-current suppression. |
| Optical Module Supply | RF Power Amplifier Bias |
Use Scenario: Generating compact, low-EMI ±5 V to ±12 V rails for laser diode drivers and transimpedance amplifiers in fiber-optic transceivers. IC Role / Device Role / Timing Role: Dual-output regulator with slew rate control and SYNC input - allows EMI filtering alignment with host system clock and minimizes jitter injection into optical timing paths. Use Value: 1.2/2.4 MHz switching with external sync (1.0–2.6 MHz) enables placement of switching noise outside critical 1–10 GHz optical data bands. | Use Scenario: Delivering stable, low-noise negative bias (e.g., −5 V to −12 V) for GaAs/GaN RF power amplifier gate control in 5G infrastructure or radar modules. IC Role / Device Role / Timing Role: Inverting regulator with precision enable (EN2), OVP, and thermal shutdown - ensures safe, sequenced turn-on and fault protection under RF load transients. Use Value: −30 V capability with 0.6 A switch and <1.5% VNEG accuracy over temperature - maintains consistent amplifier gain and linearity across operating conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DC-DC regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5071ACPZ-R7 | Higher boost/inverter switches (2.0 A / 1.2 A); same 20-lead LFCSP package; no WLCSP option. | Better suited for higher load currents (>150 mA VPOS, >75 mA VNEG) and thermally demanding environments. | Select ADP5071ACPZ-R7 when output current requirements exceed ADP5072ACBZ-R7's 1.0 A / 0.6 A limits and board space permits larger LFCSP. |
| MAX77424EWA+T | Single-chip dual-output buck-boost with fixed ±5 V outputs; no resistor programming; 2.2 MHz fixed frequency; 1.8–5.5 V input. | Limited to fixed outputs; lacks independent regulation, sequencing, or high-voltage capability - suitable only for low-voltage, low-complexity bias rails. | Choose MAX77424EWA+T only for cost-sensitive, space-constrained designs needing simple ±5 V without programmability or high-voltage support. |
Compared with ADP5072ACBZ-R7, ADP5071ACPZ-R7 delivers higher current and thermal robustness in a larger package, while MAX77424EWA+T offers integration and simplicity at the expense of flexibility, voltage range, and precision control - making ADP5072ACBZ-R7 optimal for programmable, high-voltage, low-noise dual-rail systems.
Availability
ADP5072ACBZ-R7 is available at Aetrix Electronics and suitable for precision analog instrumentation, optical sensing modules, and RF front-end biasing requiring stable component supply, full traceability, and long-term lifecycle support.
Supply support for ADP5072ACBZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The ADP5072 belongs to Analog Devices' precision dual-output DC-DC regulator product line, designed specifically for applications demanding independently programmable, low-noise, high-voltage bipolar supplies in ultra-compact footprints.
FAQ
What is the maximum positive and negative output voltage supported by the ADP5072ACBZ-R7?
The ADP5072ACBZ-R7 supports an adjustable positive output up to +35 V and an adjustable negative output down to −30 V. These limits are defined by the internal power FETs' 39 V drain-source rating and the feedback architecture - VPOS is set via resistor divider to AGND using the 0.8 V FB1 reference, while VNEG is set relative to the 1.6 V VREF pin using the 0.8 V FB2 reference offset.
How does the ADP5072ACBZ-R7 achieve independent regulation of its positive and negative outputs?
The ADP5072ACBZ-R7 achieves independent regulation through two fully separate control loops: one for the boost regulator (FB1, COMP1, SW1) and one for the inverting regulator (FB2, COMP2, SW2). Each loop uses its own error amplifier (gM = 260–340 µA/V), current-sense path, and PWM modulator - enabling simultaneous but uncorrelated adjustment of VPOS and VNEG without cross-regulation degradation.
Can the ADP5072ACBZ-R7 synchronize its switching frequency to an external clock source?
Yes, the ADP5072ACBZ-R7 supports external synchronization via the SYNC pin, accepting an input clock from 1.0 MHz to 2.6 MHz. When SYNC is driven by an external oscillator, the internal PLL locks to that frequency - allowing system-level noise filtering by aligning switching harmonics away from sensitive analog or RF bands, unlike fixed-frequency alternatives.
What package type and dimensions does the ADP5072ACBZ-R7 use, and what is its thermal rating?
The ADP5072ACBZ-R7 uses a 20-ball WLCSP package measuring 1.61 mm × 2.18 mm with 0.4 mm pitch. It is rated for a junction temperature range of −40°C to +125°C, with thermal resistance θJA = 50°C/W (4-layer PCB). Its compact size suits portable and high-density PCBs, while the specified thermal performance requires careful copper pour and thermal via design per Analog Devices' layout guidelines.
Does the ADP5072ACBZ-R7 support programmable soft start, and how is it implemented?
Yes, the ADP5072ACBZ-R7 supports resistor-programmable soft start via the SS pin. Leaving SS open yields a 4 ms soft start; connecting a resistor (e.g., 50 kΩ) from SS to AGND extends it to 32 ms. This linear ramp controls internal reference startup and output voltage rise - preventing inrush current, minimizing output overshoot, and ensuring clean power-up for downstream analog circuitry.
ADP5072ACBZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Up
- Output Configuration:
- Positive and Negative (Dual Rail)
- Topology:
- Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.85V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 35V
- Current - Output:
- 600mA, 1A
- Frequency - Switching:
- 1.2MHz, 2.4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-WLCSP (1.61x2.18)
ADP5072ACBZ-R7 FAQ
1.How can I place an order for ADP5072ACBZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5072ACBZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5072ACBZ-R7 reliable?
The price and inventory of ADP5072ACBZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5072ACBZ-R7 is usually 5 days.
3.What payment methods are accepted for ADP5072ACBZ-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5072ACBZ-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5072ACBZ-R7?
ADP5072ACBZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5072ACBZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5072ACBZ-R7?
For technical support, including ADP5072ACBZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5072ACBZ-R7 requirements.
6.How does Aetrix verify that ADP5072ACBZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5072ACBZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5072ACBZ-R7 meets industry standards.
7.What is the process for return or replacement of ADP5072ACBZ-R7?
All ADP5072ACBZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5072ACBZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5072ACBZ-R7 part is unused and in its original packaging.
Return procedure for ADP5072ACBZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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