Analog Devices Inc. ADP5075ACBZ-R7
- Part No.:
- ADP5075ACBZ-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 12-UFBGA, WLCSP
- Datasheet:
-
ADP5075ACBZ-R7.pdf
- Description:
- IC REG BCK BST ADJ 800MA 12WLCSP
- Quantity:
- Payment:

- Shipping:

Inventory:529
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADP5075ACBZ-R7 from Analog Devices is a high-performance dc-to-dc inverting regulator generating adjustable negative output rails up to 39 V below input, featuring an integrated 800 mA main switch, 1.2 MHz/2.4 MHz selectable switching frequency, and precision enable control. It operates across 2.85 V to 15 V input and supports bipolar amplifier, ADC/DAC, and RF PA bias applications.
For engineers reviewing the ADP5075ACBZ-R7 datasheet, ADP5075ACBZ-R7 pinout, ADP5075ACBZ-R7 application, or ADP5075ACBZ-R7 equivalent, this page delivers verified technical context, validated pin functions, confirmed protection features (UVLO/OCP/OVP/TSD), and real-world design implications for noise-sensitive analog and RF power supply designs.
Technical Context
The ADP5075ACBZ-R7 implements a fixed-frequency PWM-controlled inverting topology with internal 1.6 V reference and error amplifier compensation via COMP pin. Its phase-locked loop (PLL) oscillator supports pin-selectable 1.2 MHz or 2.4 MHz operation or external synchronization from 1.0 MHz to 2.6 MHz.
Slew rate control at the SW node is programmable via SLEW pin (open = fast, VREG = normal, GND = slow), directly reducing EMI without altering regulation loop dynamics. Soft start timing is resistor-programmable (4–32 ms), and precision enable thresholds (1.05 V typical) support controlled sequencing with ±0.025 V hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.85 V to 15 V - supports single-cell Li-ion, USB, and industrial 5 V/12 V rails without pre-regulation. |
| Negative Output Range | Up to VIN − 39 V - enables deep negative bias generation (e.g., −34 V from 5 V input) for CCD and RF PA stages. |
| Switch Current Limit | 800 mA typical - defines maximum sustainable load current before hiccup-mode OCP activation. |
| Switching Frequency | 1.2 MHz or 2.4 MHz (pin-selectable); 1.0–2.6 MHz sync-capable - allows EMI filtering optimization and layout compactness. |
| Reference Voltage | 1.60 V ±0.5% (25°C), ±1.5% (−40°C to +125°C) - sets feedback accuracy for stable output voltage programming. |
| Quiescent Current | 4.0 mA typical (operating), 10 µA max (shutdown) - enables low-power standby in battery-powered instrumentation. |
| Thermal Shutdown | 150°C threshold with 15°C hysteresis - protects against sustained overload or poor PCB thermal design. |
Pinout & Package
ADP5075ACBZ-R7 uses a 1.61 mm × 2.18 mm, 12-ball WLCSP package with bottom-side ball layout (ball side down). Thermal resistance θJA = 68.3°C/W (4-layer PCB), enabling high-density placement in space-constrained analog modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AVIN | System Power Supply Input | Supplies internal logic and regulators; must be decoupled with ≥3.3 µF ceramic capacitor. |
| PVIN | Inverter Power Input | Feeds inverting regulator power stage; requires ≥5.6 µF ceramic capacitor near pin. |
| SW | Switching Node | Connects to inductor and Schottky diode anode; high dv/dt node requiring minimized trace area. |
| VREG | Internal Regulator Output | 4.25 V supply for internal circuitry; requires 1.0 µF ceramic capacitor to GND. |
| SLEW | Slew Rate Control | Configures MOSFET driver slew: open (fast), VREG (normal), GND (slow) - trade-off between efficiency and EMI. |
| SS | Soft Start Timer | Resistor-to-GND sets soft start time (4–32 ms); open = fastest startup (4 ms). |
| GND | Ground Reference | Common return for AVIN, PVIN, VREG, VREF, FB, COMP, EN, SYNC/FREQ, and SLEW. |
| SYNC/FREQ | Frequency Selection/Sync Input | Low = 1.2 MHz, High = 2.4 MHz, external clock = 1.0–2.6 MHz sync - enables noise-aware system clock alignment. |
| EN | Precision Enable Input | 1.05 V threshold (±25 mV); internal 1.48 MΩ pull-down ensures default disable when floating. |
| VREF | Reference Output | 1.6 V reference for feedback network; requires 1.0 µF ceramic capacitor to GND. |
| FB | Feedback Input | Monitors output via resistor divider; 0.1 µA bias current demands ≥10× divider current for accuracy. |
| COMP | Error Amplifier Compensation | External RC network stabilizes control loop; design dependent on inductor, output cap, and load. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Slew Rate Control | Three discrete settings (fast/normal/slow) reduce EMI at SW node without compromising regulation stability. |
| Resistor-Programmable Soft Start | Adjustable 4–32 ms ramp prevents inrush current into large output capacitors during power-up. |
| Integrated Protection Suite | UVLO (2.85 V rising), OCP (880 mA typ), OVP (0.74 V at FB), TSD (150°C) - eliminates need for external fault management. |
| True Shutdown Disconnect | Load fully isolated from input during EN = low - critical for zero-leakage bias in precision analog systems. |
| Wide Input/Output Flexibility | 2.85–15 V input supports diverse sources; negative output programmable to VIN − 39 V enables multi-rail analog biasing. |
Applications
| Bipolar Amplifier Bias | ADC/DAC Reference Supply |
|---|---|
|
Use Scenario: Generating matched ±15 V rails for high-speed op-amps in data acquisition front-ends. IC Role / Device Role / Timing Role: Inverting regulator providing clean, low-noise negative rail synchronized to system clock via SYNC/FREQ pin. Use Value: Slew rate control minimizes switching noise coupling into sensitive analog signal paths, preserving SNR. |
Use Scenario: Supplying negative reference voltage for 16-bit SAR ADCs requiring stable −5 V or −12 V bias. IC Role / Device Role / Timing Role: Precision-adjustable inverter delivering regulated negative rail with <±1.5% reference accuracy over temperature. Use Value: Tight line/load regulation (0.003%/V, 0.0004%/mA) maintains ADC full-scale accuracy across varying input and load conditions. |
| RF Power Amplifier Bias | CCD Imaging Bias Supply |
|
Use Scenario: Providing −30 V bias to GaAs FETs in cellular infrastructure RF PAs operating at 1.8–2.7 GHz. IC Role / Device Role / Timing Role: High-voltage inverter supporting deep negative output with 39 V drain-source rating on internal FET. Use Value: 2.4 MHz switching enables compact LC filter design while maintaining >80% efficiency at 30 mA load (VIN = 5 V, VNEG = −30 V). |
Use Scenario: Delivering ultra-stable −18 V to −35 V bias for scientific CCD sensors in low-light astronomy cameras. IC Role / Device Role / Timing Role: Low-quiescent-current inverter (4 mA typ) with true shutdown for duty-cycled sensor biasing. Use Value: Resistor-programmable soft start prevents voltage overshoot during CCD reset cycles, avoiding pixel saturation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inverting regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5071ACPZ-R7 | Higher 1.2 A inverter switch current; 20-lead LFCSP (4 mm × 4 mm); no slew rate control. | Supports higher load currents (>500 mA) but lacks EMI-reduction features for noise-critical analog designs. | Select ADP5071ACPZ-R7 only when output current exceeds 400 mA and board area permits larger package. |
| LT3467EDD#TRPBF | Fixed 1.25 MHz frequency; 600 mA switch; 10-lead DFN (3 mm × 3 mm); no sync or slew control. | Lower integration (no internal VREG/VREF); requires external reference and compensation components. | Choose LT3467EDD#TRPBF only if cost sensitivity outweighs design simplicity and EMI performance requirements. |
Compared with ADP5075ACBZ-R7, ADP5071ACPZ-R7 offers higher current but sacrifices WLCSP size and EMI control, while LT3467EDD#TRPBF reduces feature set and increases BOM count-making ADP5075ACBZ-R7 optimal for compact, low-noise, programmable negative rail generation.
Availability
ADP5075ACBZ-R7 is available at Aetrix Electronics and suitable for bipolar amplifier biasing, precision ADC/DAC reference supplies, and RF power amplifier bias applications requiring stable component supply, tight voltage accuracy, and low-noise operation.
Supply support for ADP5075ACBZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, industrial automation, and communications markets since 1965.
The ADP5075ACBZ-R7 belongs to Analog Devices' high-efficiency inverting regulator product line, designed specifically for generating clean, programmable negative supply rails in space-constrained analog and RF subsystems.
FAQ
What is the maximum negative output voltage achievable with the ADP5075ACBZ-R7?
The ADP5075ACBZ-R7 supports an adjustable negative output down to VIN − 39 V. For example, with a 5 V input, it can generate up to −34 V; with 15 V input, up to −24 V. This is enabled by its internal 39 V-rated power FET and robust overvoltage protection at the FB pin (0.74 V threshold), ensuring safe operation across the full range.
How does the SLEW pin affect EMI and efficiency in the ADP5075ACBZ-R7?
The SLEW pin on the ADP5075ACBZ-R7 configures the MOSFET driver slew rate: open = fastest (best efficiency), VREG = normal, GND = slowest (lowest EMI). Slower slew reduces ringing and conducted emissions at the SW node but increases switching losses. This trade-off is critical in mixed-signal systems where ADC sampling windows require ultra-low noise during conversion.
Can the ADP5075ACBZ-R7 synchronize to an external clock, and what is the supported frequency range?
Yes, the ADP5075ACBZ-R7 supports external synchronization via the SYNC/FREQ pin across 1.0 MHz to 2.6 MHz. When driven by an external clock source within this range, the internal PLL locks to the input frequency, enabling precise noise spectrum placement-essential for avoiding interference in sensitive RF or high-resolution data acquisition systems.
What protection features are integrated into the ADP5075ACBZ-R7?
The ADP5075ACBZ-R7 integrates UVLO (2.85 V rising), overcurrent protection (880 mA typical), overvoltage protection (0.74 V at FB pin), and thermal shutdown (150°C with 15°C hysteresis). These features operate autonomously without external components, ensuring robust operation during input transients, short circuits, or thermal overload-critical for unattended industrial and medical equipment.
Is the ADP5075ACBZ-R7 suitable for battery-powered applications?
Yes, the ADP5075ACBZ-R7 is well-suited for battery-powered applications due to its 4.0 mA typical operating quiescent current and 10 µA maximum shutdown current. Its wide 2.85 V to 15 V input range accommodates single-cell Li-ion (3.0–4.2 V) and multi-cell configurations, while true shutdown disconnect prevents battery drain during idle periods in portable instrumentation and handheld test gear.
ADP5075ACBZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 12-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Ratiometric, Step-Up/Step-Down
- Output Configuration:
- Negative
- Topology:
- Buck-Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.85V
- Voltage - Input (Max):
- 15V
- Voltage - Output (Min/Fixed):
- Vin-39V
- Voltage - Output (Max):
- -
- Current - Output:
- 800mA
- Frequency - Switching:
- 1.2MHz, 2.4MHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-WLCSP (1.61x2.18)
ADP5075ACBZ-R7 FAQ
1.How can I place an order for ADP5075ACBZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5075ACBZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5075ACBZ-R7 reliable?
The price and inventory of ADP5075ACBZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5075ACBZ-R7 is usually 5 days.
3.What payment methods are accepted for ADP5075ACBZ-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5075ACBZ-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5075ACBZ-R7?
ADP5075ACBZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5075ACBZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5075ACBZ-R7?
For technical support, including ADP5075ACBZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5075ACBZ-R7 requirements.
6.How does Aetrix verify that ADP5075ACBZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5075ACBZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5075ACBZ-R7 meets industry standards.
7.What is the process for return or replacement of ADP5075ACBZ-R7?
All ADP5075ACBZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5075ACBZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5075ACBZ-R7 part is unused and in its original packaging.
Return procedure for ADP5075ACBZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADP5075ACBZ-R7 Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

