Analog Devices Inc. ADP5076ACBZ-R7
- Part No.:
- ADP5076ACBZ-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-UFBGA, WLCSP
- Datasheet:
-
ADP5076ACBZ-R7.pdf
- Description:
- IC REG BOOST ADJ DL 20WLCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP5076ACBZ-R7 from Analog Devices is a dual-output DC-DC switching regulator IC that independently generates a programmable positive rail up to +35 V (2.0 A boost) and a programmable negative rail down to −30 V (1.2 A inverter) from a 2.85 V–5.5 V input. It integrates both main switches, supports 1.2 MHz or 2.4 MHz switching (with external sync up to 2.6 MHz), and delivers precise sequencing control for bipolar supply systems in precision analog signal chains.
For engineers reviewing the ADP5076ACBZ-R7 datasheet, ADP5076ACBZ-R7 pinout, ADP5076ACBZ-R7 application, or ADP5076ACBZ-R7 equivalent, key selection criteria include independent output programming, out-of-phase operation for reduced input ripple, slew rate control for EMI mitigation, and WLCSP package suitability for space-constrained high-density PCBs.
Technical Context
The ADP5076ACBZ-R7 implements two independent PWM regulators: a boost stage with 2.0 A integrated MOSFET (RDS(ON) = 175 mΩ, VDS(MAX) = 39 V) and an inverting stage with 1.2 A integrated MOSFET (RDS(ON) = 350 mΩ, VDS(MAX) = 39 V). Both employ current-mode control with transconductance error amplifiers (GM = 260–340 μA/V) and feature adjustable soft start, UVLO (2.85 V rising), and thermal shutdown (150°C).
It supports three startup modes-simultaneous, VPOS-first, or VNEG-first-via the SEQ pin, and enables noise-sensitive designs through resistor-programmable slew rate (SLEW pin) and external frequency synchronization (1.0–2.6 MHz). The 20-ball WLCSP (1.61 mm × 2.18 mm) uses separate power (PVIN/PGND) and analog (AVIN/AGND) domains to minimize coupling between rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.85 V to 5.5 V - supports single-cell Li-ion, USB, or regulated 3.3 V/5 V rails without pre-regulation. |
| Positive Output Range | +35 V max - achieved via resistor divider on FB1; feedback voltage fixed at 0.8 V with ±1.5% accuracy over −40°C to +125°C. |
| Negative Output Range | −30 V max - set via FB2/VREF divider; reference voltage 1.60 V with ±1.5% accuracy across full temperature range. |
| Switching Frequency | 1.2 MHz or 2.4 MHz (pin-selectable); externally synchronizable from 1.0 MHz to 2.6 MHz - enables EMI filtering and avoids sensitive frequency bands. |
| Current Limits | Boost: 2.0–2.4 A; Inverter: 1.20–1.44 A - provides robust overload protection while maintaining regulation under transient loads. |
| Quiescent Current | 4.0 mA typical (operating), 2.2 mA typical (standby) - ensures low power loss in always-on or battery-backed systems. |
| Package | 20-ball WLCSP (1.61 mm × 2.18 mm, 0.4 mm pitch) - ultra-compact footprint ideal for portable instrumentation and optical modules. |
Pinout & Package
ADP5076ACBZ-R7 is housed in a 20-ball wafer-level chip-scale package (WLCSP) with 0.4 mm ball pitch, optimized for minimal board area and thermal performance in high-density layouts. The package supports −40°C to +125°C junction temperature operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PVIN, A1/B2 | Power Input for Inverter Regulator | Dedicated high-current path for inverter stage; decoupling required near PVIN/PGND. |
| AVIN, B1 | System Power Supply Input | Supplies internal logic, references, and gate drivers; must be clean and well-decoupled. |
| SW1, A3/B3 | Boost Regulator Switching Node | Connects to boost inductor and diode; high dv/dt node requiring tight layout and ground plane. |
| SW2, A2 | Inverting Regulator Switching Node | Connects to inverter inductor and diode; operates 180° out-of-phase with SW1 to reduce input ripple. |
| EN1, D4 | Boost Regulator Precision Enable | Threshold-based enable (1.15 V typ); internal 1.48 MΩ pull-down allows floating = disable. |
| EN2, C1 | Inverter Regulator Precision Enable | Independent threshold-based enable (1.15 V typ); enables flexible sequencing with SEQ pin. |
| SEQ, C3 | Startup Sequence Control | Selects simultaneous, VPOS-first, or VNEG-first startup; open = manual per-EN control. |
| SLEW, D2 | Driver Slew Rate Control | Open = fastest slew (best efficiency); AVIN = normal; AGND = slowest (best noise performance). |
| SS, D3 | Soft Start Programming | Open = 4 ms default; resistor to AGND extends time up to 32 ms - prevents inrush into large output caps. |
| FB1, D4 | Boost Feedback Input | Monitors VPOS via resistor divider; 0.8 V reference enables wide output range with high accuracy. |
| FB2, E2 | Inverter Feedback Input | Monitors VNEG referenced to VREF (1.60 V); enables stable negative rail regulation with matched accuracy. |
| VREF, E3 | Inverter Reference Output | 1.60 V precision reference; requires 1.0 μF ceramic capacitor to AGND for stability and noise rejection. |
| COMP1/E4, COMP2/E1 | Error Amplifier Compensation | External RC networks set loop stability for each regulator independently - critical for load step response. |
| PGND, A4/B4 | Power Ground (Boost) | High-current return path for boost stage; must be separated from AGND and connected at single point. |
| AGND, D1 | Analog Ground | Reference ground for all analog circuitry (references, FB pins, COMP pins); low-noise routing essential. |
Key Features
| Feature | Design Value |
|---|---|
| Independent Positive/Negative Output Programming | Each rail adjusted separately via FB1/FB2 resistor dividers - eliminates need for external op-amps or charge pumps in bipolar supply designs. |
| Out-of-Phase Switching Operation | SW1 and SW2 driven 180° apart - reduces input capacitor RMS current and lowers input ripple by ~30% vs. in-phase operation. |
| Programmable Slew Rate Control | Three discrete slew settings (via SLEW pin) - balances efficiency (fast) vs. EMI/noise (slow) without changing layout or components. |
| Flexible Startup Sequencing | SEQ pin configures simultaneous, VPOS-first, or VNEG-first ramp-up - meets strict sequencing requirements of ADCs, DACs, and multiplexers. |
| Resistor-Programmable Soft Start | SS pin accepts external resistor to extend soft start from 4 ms to 32 ms - prevents inrush into large output capacitors and avoids system brownouts. |
| Comprehensive Protection Suite | UVLO, OCP (per rail), OVP (at FB pins), TSD (150°C), and hiccup-mode recovery - ensures robust operation in unattended or industrial environments. |
Applications
| Bipolar Amplifier Supply | High-Voltage CCD Bias |
|---|---|
Use Scenario: Powering precision op-amps and instrumentation amplifiers requiring symmetric ±15 V rails with low noise and tight regulation. IC Role / Device Role / Timing Role: Dual-rail DC-DC converter generating isolated, independently regulated VPOS and VNEG outputs from a single low-voltage input. Use Value: Eliminates discrete charge pumps or transformer-based supplies; achieves <±1.5% output accuracy over temperature with no external trimming. |
Use Scenario: Providing programmable high-voltage bias (e.g., +24 V, −12 V) for CCD image sensors in medical or scientific imaging systems. IC Role / Device Role / Timing Role: Adjustable boost/inverter regulator delivering stable, low-ripple bias voltages with fast transient response to sensor pixel switching. Use Value: Supports wide output range (+35 V / −30 V) and enables dynamic bias adjustment via FB resistors - replaces multiple fixed-voltage modules. |
| Optical Module Power | RF Power Amplifier Bias |
Use Scenario: Generating compact, low-noise ±5 V to ±12 V rails for laser diode drivers and transimpedance amplifiers in fiber-optic transceivers. IC Role / Device Role / Timing Role: High-frequency (2.4 MHz capable) dual-output regulator minimizing solution size while meeting stringent EMI limits for telecom standards. Use Value: Slew rate control and out-of-phase operation reduce conducted emissions; WLCSP package fits within tight QSFP-DD module footprints. |
Use Scenario: Supplying gate and drain bias voltages (e.g., +10 V, −5 V) to GaAs or GaN RF power amplifiers in 5G base station front-ends. IC Role / Device Role / Timing Role: High-efficiency, thermally robust DC-DC regulator delivering stable bias under varying PA load conditions and ambient temperatures. Use Value: Integrated 2.0 A/1.2 A switches and 150°C thermal shutdown ensure reliable operation in thermally constrained RF enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DC-DC regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADP5071ACPZ-R7 | LFCSP-20 (4 mm × 4 mm); same 2.0 A/1.2 A switch ratings and feature set, but larger footprint and higher θJA (58°C/W vs. 50°C/W). | Better suited for prototyping or thermal-limited designs where WLCSP rework is impractical. | Select when board assembly process lacks WLCSP capability or thermal margin exceeds 10°C. |
| MAX17504ATP+T | Single-channel 36 V, 2.5 A step-up controller (no inverter); requires external FETs, diodes, and negative rail generation circuitry. | Requires additional components to achieve dual-rail output - increases BOM count, layout complexity, and footprint by >3×. | Choose only if design requires >35 V positive output or custom inverter topology not supported by ADP5076ACBZ-R7. |
Compared with ADP5076ACBZ-R7, ADP5071ACPZ-R7 offers identical regulation performance in a more manufacturable package, while MAX17504ATP+T demands significant external circuitry to replicate basic dual-rail functionality - making ADP5076ACBZ-R7 the optimal choice for integrated, space-constrained bipolar supply designs.
Availability
ADP5076ACBZ-R7 is available at Aetrix Electronics and suitable for high-precision analog instrumentation, optical transceiver modules, and RF power amplifier biasing requiring stable component supply, long-term lifecycle support, and guaranteed WLCSP packaging integrity.
Supply support for ADP5076ACBZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA.
The ADP5076 belongs to Analog Devices' precision dual-output DC-DC regulator product line, engineered specifically for space-constrained, noise-sensitive applications requiring independent, high-voltage bipolar rails - such as test equipment, medical imaging, and optical communications.
FAQ
What is the maximum achievable output voltage for the positive and negative rails of the ADP5076ACBZ-R7?
The ADP5076ACBZ-R7 supports a maximum positive output voltage of +35 V and a maximum negative output voltage of −30 V. These values are enabled by its integrated 2.0 A boost switch and 1.2 A inverting switch, both rated for 39 V drain-source breakdown. Output voltage is set via external resistor dividers on FB1 and FB2, referencing 0.8 V and 1.6 V internal references respectively. The ADP5076ACBZ-R7 datasheet confirms these limits under absolute maximum ratings and typical performance curves.
Does the ADP5076ACBZ-R7 support external frequency synchronization, and what is the valid input range?
Yes, the ADP5076ACBZ-R7 supports external frequency synchronization via the SYNC pin. It accepts an external clock signal from 1.0 MHz to 2.6 MHz, with minimum on/off pulse widths of 100 ns each. Logic thresholds are VH(SYNC) = 1.3 V (high) and VL(SYNC) = 0.4 V (low). When not synchronized, the ADP5076ACBZ-R7 operates at either 1.2 MHz (SYNC = low) or 2.4 MHz (SYNC = high), as confirmed in the oscillator specifications table.
How does the SEQ pin control startup sequencing on the ADP5076ACBZ-R7?
The SEQ pin on the ADP5076ACBZ-R7 determines startup behavior: open = manual enable (EN1/EN2 control each rail independently); tied to AVIN = simultaneous startup when EN2 rises; pulled low = sequenced startup (either EN1 or EN2 can initiate first rail, with the other held low). This is explicitly defined in Table 5 (Pin Function Descriptions) and the Startup Sequence section of the ADP5076ACBZ-R7 datasheet.
What is the purpose of the SLEW pin on the ADP5076ACBZ-R7, and how does it affect performance?
The SLEW pin on the ADP5076ACBZ-R7 controls the slew rate of the SW1 and SW2 driver stages to balance efficiency and EMI. Open = fastest slew (best efficiency); connected to AVIN = normal slew; connected to AGND = slowest slew (best noise/EMI performance). This function is documented in Table 5 and the Slew Rate Control section of the ADP5076ACBZ-R7 datasheet, with measured impact on conducted emissions and light-load efficiency.
Can the ADP5076ACBZ-R7 operate with only one output enabled while the other remains disabled?
Yes, the ADP5076ACBZ-R7 supports independent enable control: EN1 enables only the boost regulator (VPOS), and EN2 enables only the inverting regulator (VNEG). Either can be held below 0.4 V (shutdown threshold) while the other is active. This is confirmed by the Precision Enabling section and Absolute Maximum Ratings table in the ADP5076ACBZ-R7 datasheet, which specify individual enable thresholds and allow asymmetric operation without damage or instability.
ADP5076ACBZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-UFBGA, WLCSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Up
- Output Configuration:
- Positive and Negative
- Topology:
- Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.85V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 35V, -30V
- Current - Output:
- 2A (Switch), 1.2A (Switch)
- Frequency - Switching:
- 1.2MHz, 2.4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-WLCSP (1.61x2.18)
ADP5076ACBZ-R7 FAQ
1.How can I place an order for ADP5076ACBZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5076ACBZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5076ACBZ-R7 reliable?
The price and inventory of ADP5076ACBZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5076ACBZ-R7 is usually 5 days.
3.What payment methods are accepted for ADP5076ACBZ-R7?
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4.How is shipping managed for ADP5076ACBZ-R7?
ADP5076ACBZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5076ACBZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5076ACBZ-R7?
For technical support, including ADP5076ACBZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5076ACBZ-R7 requirements.
6.How does Aetrix verify that ADP5076ACBZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5076ACBZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5076ACBZ-R7 meets industry standards.
7.What is the process for return or replacement of ADP5076ACBZ-R7?
All ADP5076ACBZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5076ACBZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5076ACBZ-R7 part is unused and in its original packaging.
Return procedure for ADP5076ACBZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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