Analog Devices Inc. ADP5135ACPZ-R7
- Part No.:
- ADP5135ACPZ-R7
- Manufacturer:
- Analog Devices Inc.
- Package:
- 24-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADP5135ACPZ-R7.pdf
- Description:
- IC REG BCK ADJ 1.8A TRPL 24LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADP5135ACPZ-R7 from Analog Devices is a triple-output, high-efficiency buck regulator IC integrating three 1800 mA synchronous step-down converters (BUCK1/BUCK2/BUCK3) with precision enable inputs and independent open-drain power-good outputs. It operates from 3.0 V to 5.5 V input, delivers output voltages adjustable from 0.8 V to 3.8 V per channel, and supports forced PWM or auto PWM/PSM modes at 3 MHz switching frequency. It is used in compact, multi-rail power systems for FPGAs and RF chipsets.
For engineers reviewing the ADP5135ACPZ-R7 datasheet, ADP5135ACPZ-R7 pinout, ADP5135ACPZ-R7 application, or ADP5135ACPZ-R7 equivalent, key selection considerations include its 24-lead 4 mm × 4 mm LFCSP package, ±1.8% output voltage accuracy, individual ENx/PGx control per regulator, thermal shutdown (150°C), and UVLO (2.45 V falling threshold).
Technical Context
The ADP5135ACPZ-R7 implements a current-mode PWM architecture with fixed 3 MHz operation in forced PWM mode and automatic transition to power-save mode (PSM) below 100 mA load per channel. Each buck regulator features dedicated soft-start, precision enable thresholds (VENR = 0.97 V typ, 80 mV hysteresis), and active pull-down (75 Ω) for controlled output discharge.
BUCK1 and BUCK2 operate in phase; BUCK3 operates 180° out-of-phase to reduce input capacitor RMS current. All regulators share AVIN/AGND but maintain isolated power grounds (PGND1–PGND3) and independent feedback (FB1–FB3) and switching nodes (SW1–SW3), enabling flexible layout and noise isolation in multi-domain systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.0 V to 5.5 V - supports single-cell Li-ion, USB 5 V, and industrial 3.3 V/5 V rails without external pre-regulation. |
| Output Current per Channel | 1800 mA - sufficient to power core logic, I/O, and analog rails of mid-tier FPGAs and ASICs. |
| Output Voltage Accuracy | ±1.8% - ensures stable supply margins for sensitive digital loads operating near voltage limits. |
| Switching Frequency | 2.5 MHz to 3.5 MHz - enables use of small 1 µH inductors and 10–22 µF ceramic output capacitors, minimizing board area. |
| Power-Good Threshold | Falling: 85% VOUT, Rising: 94% VOUT - provides reliable sequencing and fault detection with 9% hysteresis to prevent chatter. |
| Thermal Shutdown | 150°C with 20°C hysteresis - protects against sustained overload or poor PCB thermal design while allowing safe recovery at ≤130°C. |
| Enable Threshold Hysteresis | 80 mV - prevents erratic turn-on/off during slow-rising or noisy enable signals in system-level power sequencing. |
Pinout & Package
ADP5135ACPZ-R7 is housed in a 24-lead, 4 mm × 4 mm LFCSP (Lead Frame Chip Scale Package) with exposed thermal pad. The package supports high-power density and efficient heat dissipation when soldered to a PCB ground plane via multiple vias.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1, EN2, EN3 | Dedicated regulator enable inputs | Logic-controlled activation with precision thresholds (VIH_EN = 0.9 V, VIL_EN = 0.35 V); supports daisy-chained or independent power sequencing. |
| PG1, PG2, PG3 | Open-drain power-good outputs | Monitor respective VOUTx regulation status; require external pull-up for system reset or supervisor interfacing. |
| VIN1/VIN2/VIN3, AVIN | Input supply terminals | VINx pins accept 3.0–5.5 V per channel; AVIN supplies internal analog circuitry and must be tied to VINx rails. |
| SW1/SW2/SW3 | Switching node outputs | Connect to external inductor; require low-ESR ceramic capacitors and careful layout to minimize EMI and voltage spikes. |
| FB1/FB2/FB3 | Feedback inputs | Set output voltage via resistor divider (VFB = 0.5 V); left unconnected for factory-programmed fixed-voltage variants. |
| PGND1/PGND2/PGND3 | Dedicated power grounds | Isolate high-current return paths per channel to prevent ground bounce and cross-regulator coupling. |
| MODE | Operating mode select | High = forced PWM (constant 3 MHz); Low = auto PWM/PSM (efficiency-optimized light-load behavior). |
Key Features
| Feature | Design Value |
|---|---|
| Triple 1800 mA Buck Regulators | Enables single-chip, multi-rail power for complex SoCs-eliminates need for discrete DC/DC solutions and reduces BOM count. |
| Precision Enable Inputs (VENR = 0.97 V) | Supports accurate, repeatable power-up sequencing across temperature (−40°C to +125°C) without external comparators. |
| Independent Power-Good Outputs | Allows per-rail health monitoring and fault isolation-critical for FPGA configuration, processor boot, and safety-critical subsystems. |
| 3 MHz Switching with Auto PWM/PSM | Delivers >90% peak efficiency at full load and maintains >80% efficiency down to 1 mA, extending battery life in portable devices. |
| Out-of-Phase BUCK3 Operation | Reduces input capacitor RMS current by ~30% versus in-phase operation-enables smaller, lower-cost input bulk capacitance. |
Applications
| FPGA Core & I/O Power | RF Transceiver Bias Supply |
|---|---|
|
Use Scenario: Powering Xilinx Artix-7 FPGA requiring separate 1.2 V core, 1.8 V I/O, and 3.3 V auxiliary rails. IC Role / Device Role / Timing Role: Primary PMU delivering regulated, sequenced, and monitored DC supplies to FPGA domains. Use Value: Eliminates three discrete buck ICs; reduces PCB area by 45% and simplifies layout with integrated PG/EN control. |
Use Scenario: Supplying bias voltages to LTE/5G front-end modules with strict ripple and transient response requirements. IC Role / Device Role / Timing Role: Multi-output regulator providing clean, low-noise 1.8 V PA bias and 3.3 V LNA supply with fast load-step response. Use Value: Achieves <100 µs load transient recovery and <10 mVpp output ripple-meets RF chipset spectral purity specs. |
| Portable Medical Imaging Sensor | Space-Constrained Industrial Controller |
|
Use Scenario: Powering CMOS image sensor, ADC, and microcontroller in handheld ultrasound probe. IC Role / Device Role / Timing Role: Central power management unit enabling low-quiescent, multi-voltage operation from single Li-ion cell. Use Value: Delivers 85 µA quiescent current in shutdown and >85% efficiency at 10 mA load-extends battery runtime beyond 8 hours. |
Use Scenario: Providing 1.2 V, 1.8 V, and 3.3 V rails in DIN-rail mounted PLC module with limited board real estate. IC Role / Device Role / Timing Role: High-density PMU replacing legacy discrete regulators and linear post-regulators. Use Value: Reduces solution footprint by 60% vs. dual-buck + LDO approach while maintaining ±1.8% output accuracy across temperature. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65217CRSLR | Integrated 3 buck + 4 LDOs; lower max current (1 A per buck); 2.2 MHz switching; no out-of-phase BUCK3. | Targets ARM-based embedded systems with mixed analog/digital rails; less suitable for high-current FPGA cores. | Choose for designs needing LDOs alongside bucks and lower component count-but verify 1 A per rail suffices. |
| MAX20049ATPA/VY+ | Triple 2.5 A bucks; 2.2 MHz; automotive AEC-Q100 Grade 1; no precision enable or PG per channel. | Designed for automotive infotainment and ADAS; lacks per-rail PG/EN needed for FPGA sequencing. | Prefer for harsh-environment automotive use-but requires external supervision for power-good signaling. |
Compared with TPS65217CRSLR and MAX20049ATPA/VY+, ADP5135ACPZ-R7 uniquely combines 1.8 A per buck, per-channel precision enable and power-good, 3 MHz operation, and BUCK3 phase offset-making it optimal for space-constrained, high-reliability FPGA and RF applications where sequencing integrity and efficiency across load range are critical.
Availability
ADP5135ACPZ-R7 is available at Aetrix Electronics and suitable for FPGA power delivery, RF transceiver biasing, and portable medical imaging systems requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for ADP5135ACPZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, communications, automotive, and healthcare markets since 1965.
The ADP5135ACPZ-R7 belongs to Analog Devices' micro PMU product line, engineered specifically for compact, multi-rail power management in FPGA, ASIC, and RF chipset applications where board space, sequencing fidelity, and light-load efficiency are critical.
FAQ
What is the maximum output current per channel for ADP5135ACPZ-R7?
The ADP5135ACPZ-R7 supports up to 1800 mA continuous output current per buck regulator (BUCK1, BUCK2, BUCK3) under typical thermal conditions with proper PCB layout and copper pour. Peak current limit is 2.6 A (typ), and derating applies above +85°C ambient or with insufficient thermal relief.
Does ADP5135ACPZ-R7 support adjustable output voltages?
Yes, ADP5135ACPZ-R7 supports externally adjustable outputs from 0.8 V to 3.8 V per channel using resistor dividers on FB1/FB2/FB3 pins (VFB = 0.5 V). It also offers factory-programmed fixed-voltage variants-this specific part number (ADP5135ACPZ-R7) is the adjustable version.
How does the MODE pin affect ADP5135ACPZ-R7 operation?
When MODE is high (≥1.1 V), all three buck regulators operate in forced PWM mode at ~3 MHz regardless of load. When MODE is low (≤0.4 V), each regulator independently switches between PWM mode (>100 mA load) and power-save mode (PSM) at light loads-improving efficiency below 100 mA while maintaining regulation.
What is the purpose of the separate PGND1, PGND2, and PGND3 pins on ADP5135ACPZ-R7?
PGND1, PGND2, and PGND3 provide dedicated, low-impedance return paths for each buck regulator's high-current switching loop. This separation minimizes ground bounce, prevents cross-talk between channels, and improves EMI performance-especially critical when powering noise-sensitive RF or high-speed digital circuits from the same IC.
Can ADP5135ACPZ-R7 be used in automotive applications?
ADP5135ACPZ-R7 is rated for −40°C to +125°C junction temperature and meets industrial reliability standards, but it is not AEC-Q100 qualified. For automotive applications requiring qualification, consider alternatives like MAX20049ATPA/VY+; ADP5135ACPZ-R7 remains suitable for non-safety-critical industrial or consumer-grade automotive infotainment subsystems.
ADP5135ACPZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 3
- Voltage - Input (Min):
- 3V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.8V
- Voltage - Output (Max):
- 3.8V
- Current - Output:
- 1.8A
- Frequency - Switching:
- 3MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-LFCSP (4x4)
ADP5135ACPZ-R7 FAQ
1.How can I place an order for ADP5135ACPZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADP5135ACPZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADP5135ACPZ-R7 reliable?
The price and inventory of ADP5135ACPZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADP5135ACPZ-R7 is usually 5 days.
3.What payment methods are accepted for ADP5135ACPZ-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADP5135ACPZ-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADP5135ACPZ-R7?
ADP5135ACPZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADP5135ACPZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADP5135ACPZ-R7?
For technical support, including ADP5135ACPZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADP5135ACPZ-R7 requirements.
6.How does Aetrix verify that ADP5135ACPZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADP5135ACPZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADP5135ACPZ-R7 meets industry standards.
7.What is the process for return or replacement of ADP5135ACPZ-R7?
All ADP5135ACPZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADP5135ACPZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADP5135ACPZ-R7 part is unused and in its original packaging.
Return procedure for ADP5135ACPZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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