Analog Devices Inc. ADP7104ACPZ-9.0-R7

Overview

ADP7104ACPZ-9.0-R7 from Analog Devices is a 20 V input, 500 mA, low-noise CMOS LDO regulator with fixed 9.0 V output, 15 µV_rms output noise, 350 mV dropout at full load, and reverse current protection. It delivers precision regulation for high-performance analog circuits such as PLLs, ADCs, and clock buffers where supply rail cleanliness is critical.

For engineers reviewing the ADP7104ACPZ-9.0-R7 datasheet, ADP7104ACPZ-9.0-R7 pinout, ADP7104ACPZ-9.0-R7 application, or ADP7104ACPZ-9.0-R7 equivalent, key selection considerations include its 9.0 V fixed output, LFCSP-8 package thermal performance, power-good indicator, programmable UVLO, and compatibility with 1 µF ceramic output capacitors.

Technical Context

The ADP7104ACPZ-9.0-R7 employs a PMOS pass transistor architecture enabling reverse current protection and low dropout across its 3.3 V to 20 V input range. Its error amplifier compares a stable internal reference against feedback from the SENSE/ADJ pin to regulate output voltage with ±0.8% initial accuracy and ±2% to +1% total variation over −40°C to +125°C.

It integrates digital power-good monitoring (open-drain PG pin), user-programmable undervoltage lockout via resistor-divider on EN/UVLO, foldback current limiting (775 mA typical), and thermal shutdown at 150°C with 15°C hysteresis - all operating stably with only 1 µF ceramic output capacitance.

Key Specifications

Pinout & Package

ADP7104ACPZ-9.0-R7 is housed in an 8-lead, 3 mm × 3 mm LFCSP package with exposed pad (EPAD) electrically connected to GND for enhanced thermal dissipation. The package supports PCB thermal vias directly under the EPAD to maintain junction temperature within −40°C to +125°C operating range at full 500 mA load.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with LT3045EDD-9#PBF and TPS7A4701RGWR, ADP7104ACPZ-9.0-R7 uniquely balances 500 mA output, 15 µV_rms noise, integrated PG/UVLO, and compact LFCSP-8 - making it optimal for space-constrained, sequenced, noise-sensitive analog systems.

Availability

ADP7104ACPZ-9.0-R7 is available at Aetrix Electronics and suitable for high-frequency oscillator power, precision ADC/DAC biasing, and PLL supply applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for ADP7104ACPZ-9.0-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.

The ADP7104 product line delivers high-voltage, low-noise LDOs optimized for powering noise-sensitive analog and RF circuits - targeting applications in communications infrastructure, medical imaging, and precision test equipment.

FAQ

What is the output voltage tolerance of ADP7104ACPZ-9.0-R7 over temperature and load?

The ADP7104ACPZ-9.0-R7 has ±0.8% initial accuracy at 25°C and 10 mA load. Over −40°C to +125°C and 1 mA to 500 mA load, output voltage varies from −2% to +1% of nominal 9.0 V. This ensures stable operation in industrial and automotive environments without external trimming.

Does ADP7104ACPZ-9.0-R7 require an external capacitor on the SENSE/ADJ pin?

No. ADP7104ACPZ-9.0-R7 is a fixed-output variant; the SENSE/ADJ pin is internally connected to VOUT and must be shorted to VOUT on the PCB. No external resistor divider or capacitor is needed - simplifying layout and reducing BOM count.

Can ADP7104ACPZ-9.0-R7 operate with a 1 µF ceramic output capacitor?

Yes. ADP7104ACPZ-9.0-R7 is specifically designed to be stable with a minimum 1 µF X5R/X7R ceramic capacitor (ESR ≤ 0.2 Ω). This eliminates need for larger or higher-ESR capacitors, enabling compact, low-cost, high-reliability designs.

What is the purpose of the PG pin on ADP7104ACPZ-9.0-R7?

PG (Power-Good) is an open-drain output that goes low when ADP7104ACPZ-9.0-R7 is in shutdown, thermal fault, current limit, or when VOUT drops below 90% of 9.0 V (i.e., <8.1 V). It enables system-level health monitoring and safe power sequencing.

How does the EN/UVLO pin function on ADP7104ACPZ-9.0-R7?

The EN/UVLO pin serves dual roles: high-active enable (drive >1.22 V to turn on) and programmable undervoltage lockout. With external resistors, its rising/falling thresholds can be set between 1.18 V and 1.28 V - allowing precise control of power-up timing relative to other rails in ADP7104ACPZ-9.0-R7-based systems.