Analog Devices Inc. ADRF6602ACPZ-R7

Overview

ADRF6602ACPZ-R7 from Analog Devices is a high-dynamic-range active RF mixer with integrated fractional-N PLL and VCO, operating as a receiver front-end component in cellular base station transceivers. It supports 1000–3100 MHz RF input, 1550–2150 MHz internal LO generation, delivers 6.5 dB voltage conversion gain, 30 dBm IIP3 (typ.), and 15.8 dB SSB noise figure at 2010 MHz RF with IP3SET = 3.3 V.

For engineers reviewing the ADRF6602ACPZ-R7 datasheet, ADRF6602ACPZ-R7 pinout, ADRF6602ACPZ-R7 application, or ADRF6602ACPZ-R7 equivalent, key selection criteria include RF bandwidth coverage, IIP3 programmability via IP3SET, SPI-controlled PLL configuration, and thermal stability across −40°C to +85°C for macrocell infrastructure deployment.

Technical Context

The ADRF6602ACPZ-R7 implements a silicon-germanium BiCMOS active mixer core with differential 200 Ω IF output, directly interfacing with baseband ADCs. Its fractional-N PLL uses a Σ-Δ modulator (modulus 1–2047) and programmable charge pump (250–1000 µA) to synthesize LO frequencies from a 12–160 MHz reference, supporting high-side injection and 500 MHz IF bandwidth.

LO generation relies on an integrated VCO with 2× fLO output routed through a ÷2 divider and programmable PLL divider; VTUNE is driven externally via CP and loop filter. The device supports dual-mode operation-internal PLL enabled (277 mA typical supply current) or external 1× LO applied to LOP/LON pins-with configurable LO driver enable (LODRV_EN) and PLL enable (PLL_EN) logic control.

Key Specifications

Pinout & Package

ADRF6602ACPZ-R7 is housed in a 40-lead, 6 mm × 6 mm LFCSP package with exposed paddle for thermal and electrical grounding. All GND pins (4, 7, 11, 15, 20, 21, 23, 24, 25, 28, 30, 31, 35) must be soldered to a low-impedance ground plane per datasheet layout guidance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar RF mixer with integrated synthesizer applications.

Compared with ADRF6601ACPZ-R7 and ADRF6604ACPZ-R7, the ADRF6602ACPZ-R7 uniquely balances 1000–3100 MHz RF coverage, 1550–2150 MHz LO synthesis, and 30 dBm IIP3 within a 277 mA power envelope-making it the optimal choice for mid-band 5G macrocell infrastructure requiring both spectral flexibility and thermal robustness.

Availability

ADRF6602ACPZ-R7 is available at Aetrix Electronics and suitable for cellular base station design, 5G massive MIMO radio units, and active antenna system development requiring stable component supply, full production traceability, and long-term lifecycle support.

Supply support for ADRF6602ACPZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Norwood, MA, with deep expertise in RF, microwave, and precision signal chain technologies.

The ADRF6602ACPZ-R7 belongs to Analog Devices' ADRF66xx family of highly integrated RF mixers with on-chip PLL/VCO, designed specifically for wireless infrastructure applications demanding high linearity, low phase noise, and compact footprint in macrocell and small cell base stations.

FAQ

What is the maximum RF input frequency supported by the ADRF6602ACPZ-R7?

The ADRF6602ACPZ-R7 supports an RF input frequency range of 1000 MHz to 3100 MHz (±3 dB bandwidth), verified across process, voltage, and temperature corners. At 3100 MHz, input return loss remains >−10 dB with external matching, and IIP3 is specified at 29.5 dBm (typ.) under standard test conditions (fRF = 2010 MHz, IP3SET = 3.3 V). This range fully covers LTE Bands 1, 3, 7, 38, 41 and 5G NR Bands n41, n77, and n78.

Does the ADRF6602ACPZ-R7 require external loop filter components for PLL operation?

Yes, the ADRF6602ACPZ-R7 requires an external third-order passive loop filter connected between CP (Pin 3) and VTUNE (Pin 39). The loop filter design depends on selected charge pump current (250–1000 µA), desired loop bandwidth (typically 50–200 kHz), and phase margin target. Analog Devices provides recommended filter topologies and component values in Application Note AN-1323 and the ADRF6602 evaluation board schematic (UG-422).

How does the IP3SET pin affect noise figure and linearity in the ADRF6602ACPZ-R7?

The IP3SET pin on the ADRF6602ACPZ-R7 directly controls the mixer's bias point: when left open, typical IIP3 is 30 dBm and SSB noise figure is 14.9 dB at 1760 MHz; when pulled to 3.3 V, IIP3 improves to 33.5 dBm but noise figure increases to 15.2 dB. This trade-off is implemented via internal current steering and is documented in Table 2 of the Rev. D datasheet-enabling system-level optimization without hardware modification.

Can the ADRF6602ACPZ-R7 operate with an external LO instead of its internal PLL?

Yes, the ADRF6602ACPZ-R7 supports external 1× LO injection via LOP and LON pins (Pins 38 and 37) when PLL_EN (Pin 16) is held low. In this mode, the internal PLL is powered down, reducing supply current from 277 mA to 168 mA (typ.). External LO must be 1550–2150 MHz, −6 to +6 dBm, and 50 Ω matched; the device maintains full RF/IF performance including 6.5 dB gain and 500 MHz IF bandwidth.

What is the purpose of the five separate VCC supply pins on the ADRF6602ACPZ-R7?

The ADRF6602ACPZ-R7 features five dedicated supply pins-VCC1, VCC2, VCC_LO, VCC_MIX, and VCC_V2I-to isolate noise-sensitive blocks: VCC1 powers the 3.3 V LDO, VCC2 powers the 2.5 V LDO, VCC_LO supplies the LO synthesizer, VCC_MIX powers the mixer core, and VCC_V2I drives the IF output buffers. Each requires local 100 pF + 0.1 µF decoupling per the datasheet to prevent cross-talk and ensure specified phase noise and IIP3 performance.