Analog Devices Inc. ADRF6612ACPZ-R7
- Part No.:
- ADRF6612ACPZ-R7
- Manufacturer:
- Analog Devices Inc.
- Category:
- RF Mixers
- Package:
- 48-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADRF6612ACPZ-R7.pdf
- Description:
- IC MIXER 700-3000MHZ 48LFCSP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADRF6612ACPZ-R7 from Analog Devices is a dual passive RF downconverting mixer with integrated fractional-N/integer-N PLL, dual VCOs, and high-linearity IF amplifiers. It operates across 700–3000 MHz RF, 200–2700 MHz LO, and 40–500 MHz IF bands, delivering 9.0 dB power conversion gain, 11.3 dB SSB noise figure, and +30 dBm input IP3 - enabling multiband cellular base station diversity receivers.
For engineers reviewing the ADRF6612ACPZ-R7 datasheet, ADRF6612ACPZ-R7 pinout, ADRF6612ACPZ-R7 application, or ADRF6612ACPZ-R7 equivalent, key selection criteria include its dual-channel passive mixer architecture, SPI-controlled internal LO synthesis, wideband single-ended RF interface, and 48-lead 7 mm × 7 mm LFCSP package with exposed thermal pad.
Technical Context
The ADRF6612ACPZ-R7 integrates two doubly balanced passive mixer cores with on-chip RF and LO baluns, supporting high-side or low-side LO injection without external matching. Its broadband square-wave LO amplifiers eliminate energy storage elements, reducing current draw at lower LO frequencies.
The synthesizer uses a BiCMOS-based PLL with programmable charge pump (250 µA–8 mA), sigma-delta modulator for fractional-N spurious suppression, and four VCO cores covering 1.6–5.15 GHz - all controlled via 3-wire SPI to generate LO signals from 200 MHz to 2700 MHz using a 12–320 MHz reference.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Frequency Range | 700 MHz to 3000 MHz continuous - enables single device coverage of LTE Bands 12/13/17/25/41 and TDD-LTE up to 2.7 GHz. |
| LO Generation | Internally synthesized 200–2700 MHz via integrated PLL/VCO - eliminates need for external LO source or synthesizer IC. |
| IF Output Range | 40 MHz to 500 MHz differential - supports direct connection to ADCs with 200 Ω differential input impedance. |
| Power Conversion Gain | 9.0 dB typical in high-performance mode - reduces required IF amplifier gain stages and system noise figure contribution. |
| IIP3 | +30 dBm at 1900 MHz - maintains dynamic range in presence of strong adjacent-channel blockers in dense cellular environments. |
| SSB Noise Figure | 11.3 dB - ensures sensitivity for weak signal reception in diversity receiver architectures. |
| Supply Voltage | 3.55–3.85 V (VCC1/VCC2/VCC7/VCC12) and 4.75–5.25 V (VCC3–VCC11) - requires dual-rail power design with LDO decoupling. |
| Package | 7 mm × 7 mm, 48-lead LFCSP with exposed thermal pad - mandates PCB thermal vias for junction temperature control below 150°C. |
Pinout & Package
ADRF6612ACPZ-R7 is housed in a 7 mm × 7 mm, 48-lead lead-frame chip-scale package (LFCSP) with an exposed thermal pad requiring low-impedance ground connection. Pin functions are defined per Analog Devices Rev. A datasheet, Table 10.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RFIN1 / RFIN2 | Dual RF Inputs | Single-ended 50 Ω ports; support independent diversity paths or MIMO receive chains. |
| IFOUT1± / IFOUT2± | Differential IF Outputs | DC-coupled, 300 Ω || 1.5 pF output impedance - match to transformer or ADC input with minimal external components. |
| LOOUT+ / LOOUT− | Internal LO Differential Output | Adjustable −5 to +7 dBm into 50 Ω - usable as local oscillator source for secondary mixers or clock distribution. |
| SCLK / SDIO / CS | SPI Interface | 3-wire serial port operating up to 26.3 MHz - configures PLL dividers, mixer modes, and bias settings without external logic. |
| VCOVTUNE | VCO Tuning Voltage Input | Analog control voltage (0–3.3 V) for manual VCO calibration or external loop filter integration. |
| REFIN | Reference Clock Input | Single-ended CMOS input accepting 12–320 MHz - supports common telecom clocks (e.g., 122.88 MHz, 30.72 MHz). |
| GND / EPAD | Ground & Thermal Pad | 12 dedicated GND pins plus exposed pad - must be connected to solid internal ground plane with ≥12 thermal vias for θJC = 1.62°C/W. |
Key Features
| Feature | Design Value |
|---|---|
| Dual Passive Mixer Cores | High-linearity, doubly balanced topology provides >45 dB LO-to-RF leakage rejection and >22 dB RF-to-IF isolation across full bandwidth. |
| Integrated PLL/VCO System | Four VCO cores with sigma-delta fractional-N synthesis achieve −223 dBc/Hz figure-of-merit and <0.87°rms integrated phase noise (1 kHz–40 MHz). |
| Programmable Operating Modes | High-Performance Mode (9.0 dB gain, 11.3 dB NF) and High-Efficiency Mode (8.7 dB gain, 2.0 W dissipation) selectable via SPI register. |
| Single-Ended RF Interface | On-chip RF baluns enable optimal 50 Ω match from 700–3000 MHz - eliminates discrete balun components and layout sensitivity. |
| Flexible LO Injection | Supports both high-side and low-side LO injection - simplifies frequency planning for FDD/TDD systems and avoids image interference. |
| Robust Power Architecture | Dedicated LDOs for SPI (2.5 V), PLL (3.3 V), and VCO (3.7 V) rails reduce supply coupling and improve spectral purity. |
Applications
| Cellular Base Station Diversity Receiver | Wideband Radio Link Downconverter |
|---|---|
|
Use Scenario: Dual-path receive chain in macrocell BTS handling simultaneous LTE FDD and TDD bands. IC Role / Device Role / Timing Role: Dual-channel RF-to-IF downconverter with integrated LO synthesis - replaces discrete mixer + PLL + VCO solution. Use Value: Reduces BOM count by ≥7 components per path while maintaining >30 dBm IIP3 and <11.5 dB NF across 700–2700 MHz. |
Use Scenario: Point-to-point microwave backhaul unit requiring 500 MHz instantaneous bandwidth and high blocker tolerance. IC Role / Device Role / Timing Role: Wideband passive mixer with programmable LO generation - enables flexible IF placement and multi-standard support. Use Value: Achieves −153 dBc/Hz IF phase noise under 10 dBm blocker condition, preserving EVM in 256-QAM modulation. |
| Multimode Cellular Picocell | Small Cell Femtocell Front-End |
|
Use Scenario: Indoor enterprise picocell supporting LTE, WCDMA, and GSM across multiple frequency tiers. IC Role / Device Role / Timing Role: Dual-mixer front-end with SPI-configurable LO and IF bandwidth - enables software-defined band switching. Use Value: Single ADRF6612ACPZ-R7 covers all major cellular bands (700–2700 MHz) without hardware reconfiguration. |
Use Scenario: Residential femtocell with stringent power and size constraints requiring high integration. IC Role / Device Role / Timing Role: Integrated mixer + synthesizer + IF buffer - eliminates external VCO, loop filter, and IF amplifiers. Use Value: Cuts PCB area by 45% vs. discrete solution and lowers quiescent current to 210 mA in high-efficiency mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-mixer-with-synthesizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADRF6614ACPZ-R7 | Wider RF range (300–3800 MHz), higher LO max (3200 MHz), +32 dBm IIP3, but larger 9 mm × 9 mm package. | Better suited for sub-1 GHz IoT gateways and 3.5 GHz CBRS deployments where extended low-end coverage is critical. | Select ADRF6614ACPZ-R7 only when RF band extends below 700 MHz or above 3000 MHz; otherwise ADRF6612ACPZ-R7 offers superior cost and footprint efficiency. |
| MAX19997AETX+ | Single-channel mixer, no integrated PLL/VCO - requires external synthesizer; 2.7–3.8 GHz RF, +28 dBm IIP3, 11.5 dB NF. | Applicable where LO is already available (e.g., shared synthesizer across multiple receivers) and dual-channel operation is not needed. | Choose MAX19997AETX+ only in legacy designs with existing LO infrastructure; ADRF6612ACPZ-R7 provides full integration and dual-path capability. |
Compared with ADRF6614ACPZ-R7 and MAX19997AETX+, the ADRF6612ACPZ-R7 delivers optimal balance of dual-channel functionality, 700–3000 MHz coverage, integrated synthesis, and compact 7 mm × 7 mm footprint - making it the preferred choice for space-constrained multiband cellular infrastructure.
Availability
ADRF6612ACPZ-R7 is available at Aetrix Electronics and suitable for multiband cellular base stations, wideband radio links, picocell femtocells, and small cell front-ends requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for ADRF6612ACPZ-R7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, headquartered in Wilmington, MA.
The ADRF6612ACPZ-R7 belongs to Analog Devices' RadioVerse™ portfolio of highly integrated RF transceivers and front-end ICs, designed specifically for cellular infrastructure, wireless backhaul, and broadband communications equipment.
FAQ
What is the RF frequency range supported by the ADRF6612ACPZ-R7?
The ADRF6612ACPZ-R7 supports a continuous RF input frequency range from 700 MHz to 3000 MHz. This enables coverage of major cellular bands including LTE Bands 12/13/17 (700 MHz), Band 4 (1700/2100 MHz), Band 41 (2500 MHz), and TDD-LTE up to 2700 MHz. Performance metrics such as IIP3 and noise figure are characterized across this full span.
Does the ADRF6612ACPZ-R7 require an external LO source?
No, the ADRF6612ACPZ-R7 does not require an external LO source. It integrates a complete fractional-N/integer-N PLL with four VCO cores and programmable dividers, generating LO signals from 200 MHz to 2700 MHz directly from a 12–320 MHz reference input. The ADRF6612ACPZ-R7 can also accept external LO via EXTVCOIN± pins if needed.
How many RF and IF channels does the ADRF6612ACPZ-R7 support?
The ADRF6612ACPZ-R7 supports two independent RF receive channels (RFIN1 and RFIN2) and two corresponding differential IF output channels (IFOUT1± and IFOUT2±). Each channel includes dedicated mixer core, LO path, and IF buffer - enabling true diversity reception or parallel MIMO signal processing without cross-talk.
What package type and thermal requirements apply to the ADRF6612ACPZ-R7?
The ADRF6612ACPZ-R7 uses a 7 mm × 7 mm, 48-lead LFCSP package with an exposed thermal pad. To maintain junction temperature ≤150°C, the exposed pad must be soldered to a solid internal ground plane with ≥12 thermal vias (0.3 mm diameter, 1.0 mm pitch). Thermal resistance is specified as θJC = 1.62°C/W.
Can the ADRF6612ACPZ-R7 operate in both high-performance and low-power modes?
Yes, the ADRF6612ACPZ-R7 supports two configurable operating modes via SPI register control: High-Performance Mode (9.0 dB gain, 11.3 dB NF, 2.7 W dissipation) and High-Efficiency Mode (8.7 dB gain, 10.7 dB NF, 2.0 W dissipation). Mode selection allows trade-offs between linearity, noise, and power consumption based on system-level requirements.
ADRF6612ACPZ-R7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- RF Type:
- -
- Frequency:
- 700MHz ~ 3GHz
- Number of Mixers:
- 1
- Gain:
- 15dB
- Noise Figure:
- 10.7dB
- Secondary Attributes:
- -
- Current - Supply:
- 260mA
- Voltage - Supply:
- 3.5V ~ 5.25V
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-LFCSP (7x7)
ADRF6612ACPZ-R7 FAQ
1.How can I place an order for ADRF6612ACPZ-R7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADRF6612ACPZ-R7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADRF6612ACPZ-R7 reliable?
The price and inventory of ADRF6612ACPZ-R7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADRF6612ACPZ-R7 is usually 5 days.
3.What payment methods are accepted for ADRF6612ACPZ-R7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADRF6612ACPZ-R7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADRF6612ACPZ-R7?
ADRF6612ACPZ-R7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADRF6612ACPZ-R7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADRF6612ACPZ-R7?
For technical support, including ADRF6612ACPZ-R7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADRF6612ACPZ-R7 requirements.
6.How does Aetrix verify that ADRF6612ACPZ-R7 is sourced from the original manufacturer or authorized distributors?
All ADRF6612ACPZ-R7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADRF6612ACPZ-R7 meets industry standards.
7.What is the process for return or replacement of ADRF6612ACPZ-R7?
All ADRF6612ACPZ-R7 units undergo pre-shipment inspection (PSI). If there is an issue with ADRF6612ACPZ-R7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADRF6612ACPZ-R7 part is unused and in its original packaging.
Return procedure for ADRF6612ACPZ-R7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADRF6612ACPZ-R7 Tags

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MAX2671EUT+T
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MAX2681EUT+T
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ADE-1ASK+
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ADE-1L+
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