Analog Devices Inc. ADRF6658BCPZ-RL7
- Part No.:
- ADRF6658BCPZ-RL7
- Manufacturer:
- Analog Devices Inc.
- Category:
- RF Mixers
- Package:
- 48-WFQFN Exposed Pad, CSP
- Datasheet:
-
ADRF6658BCPZ-RL7.pdf
- Description:
- IC MIXER DUAL
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ADRF6658BCPZ-RL7 from Analog Devices is a wideband dual-channel RF downconverter IC integrating two active Gilbert-cell mixers and two digitally controlled IF amplifiers (DGAs) in a single 48-lead LFCSP package. It operates from 690 MHz to 3.8 GHz RF input, delivers −5 dB to +26.5 dB voltage conversion gain, achieves 29 dBm input IP3 at minimum DGA gain, and supports cellular base station receiver architectures requiring high channel isolation (52 dB) and fast power-up (100 ns).
For engineers reviewing the ADRF6658BCPZ-RL7 datasheet, ADRF6658BCPZ-RL7 pinout, ADRF6658BCPZ-RL7 application, or ADRF6658BCPZ-RL7 equivalent, this device serves as a key component in multi-carrier wireless infrastructure receivers where simultaneous dual-band downconversion, programmable balun tuning, and SPI/parallel gain control are required for W-CDMA, LTE, and WiMAX front-end designs.
Technical Context
The ADRF6658BCPZ-RL7 implements two independent doubly balanced mixer cores with integrated tunable RF baluns, enabling harmonic suppression and out-of-band rejection before signal mixing. Each channel features a 300 Ω differential mixer output impedance matched to a 100 Ω differential DGA input via external dc-blocking capacitors and LC interstage filters.
Its IF DGAs-based on ADL5201/ADL5202 architecture-provide 0.5 dB gain steps over a 31.5 dB range, with <0.05 dB gain conformance error and <0.5° phase conformance error across adjacent steps. Control is supported via 3-wire SPI (32-bit shift register with register addressing) or independent 6-bit parallel ports (A0–A5 and B0–B5) with latch enable functionality.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Input Frequency Range | 690 MHz to 3.8 GHz - enables coverage of PCS, DCS, LTE Bands 1–40, and TDD-LTE spectrum without external preselection |
| Voltage Conversion Gain Range | −5 dB to +26.5 dB - provides full dynamic range control for variable IF signal levels in multi-standard receivers |
| Input IP3 (High Linearity Mode) | 29 dBm at minimum DGA gain - ensures robust interference rejection in dense spectral environments like urban macrocells |
| Channel Isolation | 52 dB - prevents crosstalk between dual receive paths in MIMO or diversity configurations |
| Power-Up Time | 100 ns typical after CHAEN/CHBEN assertion - supports rapid channel switching in time-division duplex (TDD) systems |
| Differential IF Output Impedance | 100 Ω - simplifies interface to ADC drivers or baseband filters without external matching networks |
| Total Supply Current (Dual Rx, High Linearity) | 440 mA - optimized for high-performance operation while maintaining thermal feasibility in compact RF modules |
Pinout & Package
ADRF6658BCPZ-RL7 is housed in a 7 mm × 7 mm, 48-lead lead-frame chip-scale package (LFCSP) with exposed pad (EP) for thermal management. Pin assignments follow a defined analog/digital partitioning with dedicated AGND returns for MIXAVDD, MIXBVDD, DGAAVDD, DGABVDD, LOVDD, and DVDD domains.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| MIXARFIN / MIXBRFIN | Single-ended 50 Ω RF inputs | Accepts direct connection to antenna or filter outputs; internal baluns convert to differential for mixer core |
| MIXAOUT+/MIXAOUT− / MIXBOUT+/MIXBOUT− | Differential mixer outputs | 300 Ω impedance; require external pull-up inductors tied to MIXAVDD/MIXBVDD for proper biasing and bandwidth control |
| DGAAIN+/DGAAIN− / DGABIN+/DGABIN− | Differential DGA inputs | 300 Ω impedance; dc-coupled interface to mixer outputs; matched via external LC interstage filter |
| IFAOUT+/IFAOUT− / IFBOUT+/IFBOUT− | Differential IF outputs | 100 Ω fixed impedance; directly drives ADC input stages or IF filters without series termination |
| CHAEN / CHBEN | Channel enable controls | Asynchronous hardware power-down pins allowing independent channel activation/deactivation with 100 ns latency |
| LATCHA / LATCHB | Parallel port latch controls | Enable synchronous loading of 6-bit DGA gain codes (A0–A5 / B0–B5) into respective amplifier registers |
| DATA / CLK / LE / SDO | SPI serial interface | 32-bit shift register with 4-bit address decoding; supports daisy-chaining and readback of all 16 configuration registers |
Key Features
| Feature | Design Value |
|---|---|
| Programmable RF baluns | Register-controlled cutoff tuning (CIN/COUT bits) suppresses harmonics and improves input return loss across 690–3800 MHz band |
| Independent channel power management | Hardware CHAEN/CHBEN pins and register-based mixer enable bits allow per-channel standby, sleep, or active modes |
| Dual-control DGA interface | Supports both SPI programming and latch-enabled parallel gain setting for real-time IF gain adjustment in closed-loop systems |
| Wide IF bandwidth | 520 MHz upper cutoff frequency enables direct sampling of wideband IF signals up to 260 MHz complex bandwidth |
| Low-noise, high-linearity trade-off control | V-to-I bias register (DB24:DB22) dynamically adjusts mixer transconductance to optimize IIP3 vs. NF for specific signal conditions |
Applications
| Cellular Base Station Receiver | Active Antenna System (AAS) |
|---|---|
Use Scenario: Dual-band, multi-carrier W-CDMA/LTE receiver in macrocell BTS with digital predistortion feedback path. IC Role / Device Role / Timing Role: Primary RF-to-IF downconverter providing simultaneous I/Q processing for two independent receive chains with shared LO resources. Use Value: 52 dB channel isolation prevents intermodulation between carriers, while 29 dBm IIP3 maintains ACLR compliance under high-power blocker conditions. |
Use Scenario: Integrated transceiver module in 5G mMIMO active antenna unit with beamforming-capable dual-Rx front end. IC Role / Device Role / Timing Role: Wideband dual downconverter enabling real-time calibration and channel estimation across 3.3–3.8 GHz NR bands. Use Value: 100 ns channel enable time supports fast TDD slot switching; programmable baluns compensate for antenna element mismatch across wide bandwidth. |
| PTP Radio Link Downconverter | Wireless LAN Infrastructure |
Use Scenario: High-capacity point-to-point microwave backhaul operating in 5.8 GHz unlicensed band with adjacent-channel interference. IC Role / Device Role / Timing Role: Dual-path IF extraction stage converting RF to low-IF for digitization and symbol timing recovery. Use Value: −50 dBc RF-to-IF leakage and −70 dBc intermodulation spurs ensure clean IF spectrum for high-order QAM demodulation. |
Use Scenario: Dual-band 2.4/5 GHz Wi-Fi 6 access point supporting MU-MIMO with concurrent 2×2 uplink/downlink streams. IC Role / Device Role / Timing Role: Front-end downconverter for secondary receive chain handling legacy 2.4 GHz band while primary chain handles 5 GHz. Use Value: Flexible 3.3 V single-supply operation and low 260 mA power consumption in low-power mode reduce thermal load in compact AP enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel RF downconverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADRF6612ACPZ-R7 | Single-channel architecture; 700 MHz–2.7 GHz RF range; no integrated IF DGAs (requires external amplification) | Suitable only for single-path receivers; lacks dual-channel isolation and integrated gain control | Select when cost-sensitive single-band designs prioritize footprint reduction over dual-path flexibility |
| LMX2594RHAT | Wideband PLL/VCO with integrated RF divider; no mixer or IF amplification functions | Provides LO synthesis only; requires external mixers and IF conditioning circuitry | Select when precise LO generation is needed alongside discrete mixer/DGA selection for custom performance tuning |
Compared with ADRF6658BCPZ-RL7, the ADRF6612ACPZ-R7 reduces integration but sacrifices dual-path capability and IF gain programmability, while the LMX2594RHAT addresses LO sourcing only and increases system complexity by requiring external signal path components.
Availability
ADRF6658BCPZ-RL7 is available at Aetrix Electronics and suitable for cellular infrastructure, active antenna systems, and point-to-point radio link designs requiring stable component supply, long-term lifecycle support, and traceable sourcing for production ramp.
Supply support for ADRF6658BCPZ-RL7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and RF IC design, founded in 1965 and headquartered in Wilmington, MA.
The ADRF6658BCPZ-RL7 belongs to Analog Devices' RadioVerse™ portfolio of highly integrated RF transceivers and front-end ICs, engineered specifically for wireless infrastructure applications demanding wide instantaneous bandwidth, high linearity, and flexible digital control.
FAQ
What is the operating temperature range for the ADRF6658BCPZ-RL7?
The ADRF6658BCPZ-RL7 is specified to operate across −40°C to +105°C, making it suitable for deployment in outdoor base station cabinets and active antenna units exposed to extreme environmental conditions. This extended range is validated across all key parameters including gain flatness, IP3, and noise figure, ensuring consistent performance in both arctic and desert deployments.
Does the ADRF6658BCPZ-RL7 support both differential and single-ended LO inputs?
Yes, the ADRF6658BCPZ-RL7 supports both differential and single-ended LO configurations via LOIN+ and LOIN− pins. In differential mode, both pins accept ac-coupled signals; in single-ended mode, LOIN+ receives the signal while LOIN− is ac-coupled to ground. The internal LO buffer automatically adapts to either topology without external reconfiguration.
How is gain controlled in the ADRF6658BCPZ-RL7 IF amplifiers?
The ADRF6658BCPZ-RL7 IF amplifiers support two independent gain control methods: a 3-wire SPI interface (32-bit word with 4-bit register address) and dual 6-bit parallel ports (A0–A5 and B0–B5) with dedicated LATCHA/LATCHB strobes. Both interfaces provide 0.5 dB steps over a 31.5 dB range, with identical gain conformance and phase accuracy specifications.
What package type and thermal characteristics does the ADRF6658BCPZ-RL7 have?
The ADRF6658BCPZ-RL7 uses a 7 mm × 7 mm, 48-lead LFCSP package with exposed pad (EP), achieving a thermal resistance θJA of 27.26°C/W when the EP is soldered to a low-impedance PCB ground plane using an array of vias. This enables reliable operation at full 440 mA current draw in high-density RF modules without forced air cooling.
Can the ADRF6658BCPZ-RL7 be used in low-power applications?
Yes, the ADRF6658BCPZ-RL7 offers multiple low-power operating modes: low power mode draws 260 mA total (vs. 440 mA in high linearity mode), and standby mode reduces current to 65 mA. Additionally, individual channels can be disabled via CHAEN/CHBEN pins or register control, enabling dynamic power scaling in burst-mode or TDD-based systems.
ADRF6658BCPZ-RL7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad, CSP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- RF Type:
- Cellular
- Frequency:
- 690MHz ~ 3.8GHz
- Number of Mixers:
- 2
- Gain:
- 26.5dB
- Noise Figure:
- -
- Secondary Attributes:
- -
- Current - Supply:
- 440mA
- Voltage - Supply:
- 3.3V
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-LFCSP (7x7)
ADRF6658BCPZ-RL7 FAQ
1.How can I place an order for ADRF6658BCPZ-RL7 through Aetrix?
Please submit a Request for Quotation (RFQ) for ADRF6658BCPZ-RL7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADRF6658BCPZ-RL7 reliable?
The price and inventory of ADRF6658BCPZ-RL7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADRF6658BCPZ-RL7 is usually 5 days.
3.What payment methods are accepted for ADRF6658BCPZ-RL7?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADRF6658BCPZ-RL7 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADRF6658BCPZ-RL7?
ADRF6658BCPZ-RL7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADRF6658BCPZ-RL7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADRF6658BCPZ-RL7?
For technical support, including ADRF6658BCPZ-RL7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADRF6658BCPZ-RL7 requirements.
6.How does Aetrix verify that ADRF6658BCPZ-RL7 is sourced from the original manufacturer or authorized distributors?
All ADRF6658BCPZ-RL7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADRF6658BCPZ-RL7 meets industry standards.
7.What is the process for return or replacement of ADRF6658BCPZ-RL7?
All ADRF6658BCPZ-RL7 units undergo pre-shipment inspection (PSI). If there is an issue with ADRF6658BCPZ-RL7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADRF6658BCPZ-RL7 part is unused and in its original packaging.
Return procedure for ADRF6658BCPZ-RL7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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