Analog Devices Inc. ADRV-DPD1/PCBZ

Overview

ADRV-DPD1/PCBZ from Analog Devices is a 2 × 2 MIMO small cell radio reference design board featuring the AD9375 RF transceiver with integrated digital predistortion (DPD), SKY66297-11 power amplifiers, and full JESD204B-to-antenna signal chain. It delivers 24 dBm output per path in LTE Band 7 FDD at 20 MHz bandwidth, operates from a single 12 V supply, and targets 250 mW RF output per antenna in compact base station applications.

For engineers reviewing the ADRV-DPD1/PCBZ datasheet, ADRV-DPD1/PCBZ pinout, ADRV-DPD1/PCBZ application, or ADRV-DPD1/PCBZ equivalent, this evaluation kit supports rapid prototyping of LTE small cell radios with FPGA-based baseband processing, DPD algorithm validation, and RF path characterization - requiring no custom PCB design for initial system integration.

Technical Context

The ADRV-DPD1/PCBZ implements a complete 2×2 MIMO radio architecture centered on the AD9375 transceiver, which integrates dual RF transmitters and receivers, JESD204B SerDes interfaces, and real-time DPD engine. It pairs with two SKY66297-11 PAs and two LNAs, duplex filters, and an ADP5054 dc/dc power solution to deliver full RF front-end functionality.

System clocking relies on an AD9528 clock generator on the interposer board (ADRV-INTERPOS1/PCBZ), supporting dual reference inputs (10 MHz or 30.72 MHz) and generating synchronized clocks for the AD9375, FPGA, and observation receiver paths. The board interfaces exclusively via high-pin-count (HPC) FMC connectors to Xilinx Zynq-7000 SoC platforms such as EVAL-TPG-ZYNQ3.

Key Specifications

Availability

ADRV-DPD1/PCBZ is available at Aetrix Electronics and suitable for LTE small cell development, wireless infrastructure prototyping, and digital predistortion algorithm validation requiring stable component supply, traceable sourcing, and long-term evaluation kit availability.

Supply support for ADRV-DPD1/PCBZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving communications, industrial, automotive, and aerospace markets with precision RF and data conversion technologies.

The ADRV-DPD1/PCBZ belongs to Analog Devices' ADRV (Analog Devices RadioVerse) reference design platform, engineered specifically to accelerate development of 4G/5G small cell radios by integrating RF, power, clocking, and FPGA interfacing into validated, production-ready hardware.

FAQ

What is the ADRV-DPD1/PCBZ used for?

The ADRV-DPD1/PCBZ is a fully integrated 2×2 MIMO small cell radio reference design used to prototype and validate LTE FDD base stations. It enables engineers to evaluate the AD9375 transceiver's DPD performance, characterize RF front-end linearity, and develop FPGA-based baseband processing - all without designing custom RF hardware. The ADRV-DPD1/PCBZ supports rapid iteration from lab testing to pre-deployment system verification.

Which FPGA platforms is the ADRV-DPD1/PCBZ compatible with?

The ADRV-DPD1/PCBZ interfaces exclusively via HPC FMC to Xilinx Zynq-7000 SoC evaluation boards, including the EVAL-TPG-ZYNQ3, EK-Z7-ZC706 Rev 1.2, and Avnet AES-Z7-JESD3-G Rev 1.2. It requires the Zynq's dual-core ARM Cortex-A9 running Linux and relies on the interposer board (ADRV-INTERPOS1/PCBZ) for clock distribution and power sequencing. The ADRV-DPD1/PCBZ does not support non-Zynq or non-FMC carrier platforms.

Does the ADRV-DPD1/PCBZ include digital predistortion capability?

Yes - the ADRV-DPD1/PCBZ leverages the embedded DPD engine inside the AD9375 transceiver, enabling real-time correction of PA nonlinearities. The included AD9375 Small Cell Evaluation Software (SCES) provides dedicated DPD setup, coefficient loading, and convergence monitoring. The ADRV-DPD1/PCBZ validates DPD performance using the SKY66297-11 PAs and supports closed-loop adaptation with observation receiver feedback paths.

What RF bands and standards does the ADRV-DPD1/PCBZ support out of the box?

The ADRV-DPD1/PCBZ is factory-configured for LTE FDD Band 7 (2500–2570 MHz uplink / 2620–2690 MHz downlink) at 20 MHz channel bandwidth. Its RF front-end - including duplex filters, LNAs, and SKY66297-11 PAs - is optimized for this band. While the AD9375 transceiver supports wider frequency ranges (300 MHz–6 GHz), full reconfiguration for other bands requires matching RF component changes and calibration; the ADRV-DPD1/PCBZ hardware itself is fixed for Band 7 operation.

Is external clocking required for the ADRV-DPD1/PCBZ to operate?

Yes - the ADRV-DPD1/PCBZ requires an external reference clock applied to the interposer board (ADRV-INTERPOS1/PCBZ) at either J8 (REF_A, default 10 MHz) or J13 (REF_B, default 30.72 MHz). These clocks drive the AD9528 clock generator, which synthesizes all internal clocks for the AD9375, FPGA, and observation receiver. Without a valid reference signal meeting amplitude (380–1200 mVp-p into 100 Ω) and waveform (sine or square) specs, PLL lock fails and the ADRV-DPD1/PCBZ cannot initialize.