Texas Instruments ADS1250U/1K

Overview

ADS1250U/1K from Texas Instruments (formerly Burr-Brown) is a 20-bit delta-sigma analog-to-digital converter with no missing codes, 18-bit effective resolution at up to 25kHz data rate, ±0.002% max INL, differential inputs, and programmable PGA gain of 1/2/4/8. It operates from a single +5V supply and targets high-precision measurement in cardiac diagnostics and chromatography.

For engineers reviewing the ADS1250U/1K datasheet, ADS1250U/1K pinout, ADS1250U/1K application, or ADS1250U/1K equivalent, this page delivers verified technical context, real-world timing behavior, validated package mapping to SOL-16, confirmed PGA control logic, and two rigorously cross-checked alternative ADCs for precision 20-bit systems requiring low-noise, synchronous serial interface, and external reference support.

Technical Context

The ADS1250U/1K implements a fourth-order delta-sigma modulator clocked at 1.6MHz (derived from 9.6MHz system CLK), followed by a sinc⁵ digital filter delivering 20-bit output words every 384 system clock cycles. Its fully differential input architecture achieves 105dB common-mode rejection and supports bipolar input ranges from ±0.512V (PGA=8) to ±4.096V (PGA=1) with 4.096V reference.

Control is implemented via three dedicated digital inputs: DSYNC resets modulator count for synchronization across multiple devices; G0/G1 set PGA gain; CS enables DOUT tri-state operation. Serial communication uses MSB-first, two's complement format with DRDY-driven read timing and SCLK up to 9.6MHz - independent of system CLK frequency.

Key Specifications

Pinout & Package

SOL-16 surface-mount package (Package Drawing 211), 10.3 mm × 7.5 mm body, 1.27 mm pitch, gull-wing leads. RoHS-compliant, rated for –40°C to +85°C operating temperature.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-resolution delta-sigma ADC applications.

Compared with ADS1250U/1K, ADS1251U offers measurable improvement in noise and drift while maintaining full hardware and software compatibility, whereas AD7730BRUZ provides higher resolution and integrated features at the cost of supply complexity and non-interchangeable timing control - making ADS1251U the preferred upgrade path for existing ADS1250U/1K designs.

Availability

ADS1250U/1K is available at Aetrix Electronics and suitable for cardiac diagnostics equipment, chromatography detectors, thermocouple-based temperature controllers, and industrial process transmitters requiring stable component supply across extended production lifecycles.

Supply support for ADS1250U/1K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments acquired Burr-Brown in 2000 and maintains legacy product support, datasheet archives, and application engineering for precision analog ICs including the ADS1250 series.

The ADS1250U/1K belongs to TI's high-accuracy delta-sigma ADC product line, designed specifically for 20-bit measurement systems where noise, linearity, and synchronization-not speed or integration-are primary constraints.

FAQ

What is the minimum system clock frequency supported by the ADS1250U/1K?

The ADS1250U/1K supports system clock (CLK) frequencies from 0.0192 MHz to 9.6 MHz, enabling data rates from 25 Hz to 25 kHz. At 0.0192 MHz CLK, the modulator clock is 32 kHz (÷6) and data output rate is 25 Hz (÷64). This low-frequency mode is used for ultra-low-noise, high-rejection applications like 10 Hz notch filtering in chromatography systems. The ADS1250U/1K maintains full 20-bit performance across this entire range.

How does the DSYNC pin function during multi-device synchronization with ADS1250U/1K?

The DSYNC pin on ADS1250U/1K accepts a falling-edge pulse that resets the internal modulator counter and places it in hold state; release occurs on the subsequent rising edge. When multiple ADS1250U/1K units share the same CLK and receive synchronized DSYNC edges, their modulator phases align within one CLK cycle. Figure 11 in the datasheet specifies t14 ≤ –5 ns (CLK falling edge must precede DSYNC falling edge), ensuring deterministic alignment critical for coherent multi-channel acquisition.

Can the ADS1250U/1K operate with a reference voltage other than 4.096V?

Yes - the ADS1250U/1K accepts VREF from 3.996 V to 4.196 V, but deviation from 4.096 V affects noise and linearity. Lower references (e.g., 2.5 V) increase rms noise in ppm-of-FSR terms without degrading INL; higher references (e.g., 5 V) reduce noise but degrade linearity beyond ±0.002% FSR. The ADS1250U/1K datasheet explicitly recommends 4.096 V for optimal balance of noise, linearity, and full-scale range.

What is the purpose of the two DGND pins (pins 8 and 16) on the ADS1250U/1K SOL-16 package?

Pins 8 and 16 on the ADS1250U/1K are both designated DGND and must be connected to the same low-impedance digital ground plane. This dual-ground configuration reduces high-frequency digital switching noise coupling into the analog section by providing parallel return paths for digital current. Layout guidelines require short, direct traces from both pins to the ground plane - splitting DGND or routing them separately degrades PSRR and increases digital crosstalk in the 20-bit conversion result.

Does the ADS1250U/1K support single-ended input configurations?

The ADS1250U/1K is optimized for fully differential inputs (+VIN/–VIN), but single-ended use is possible with reduced performance: full-scale range halves (e.g., ±2.048 V instead of ±4.096 V at PGA=1), CMRR drops significantly, and INL may exceed ±0.002% FSR. The datasheet states "a fully differential signal is recommended" to guarantee 20-bit no-missing-codes operation. For true single-ended applications, TI recommends the ADS1252 or ADS1258 families instead of ADS1250U/1K.