Texas Instruments ADS1288IRHBR
- Part No.:
- ADS1288IRHBR
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
ADS1288IRHBR.pdf
- Description:
- Low-power, 32-bit two-channel
- Quantity:
- Payment:

- Shipping:

Inventory:3,000
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Product details
Overview
ADS1288IRHBR from Texas Instruments is a 32-bit delta-sigma analog-to-digital converter with integrated programmable gain amplifier (PGA), designed for seismic data acquisition systems. It delivers 122dB typical dynamic range at 500SPS, <–120dB THD, and 120dB CMRR, operating from ±2.5V, 3.3V, or 5V analog supplies. Its dual-channel multiplexer, clock error compensation (7.45ppb accuracy), and flexible sinc+FIR+IIR digital filtering support geophone and hydrophone interfacing in battery-powered field instrumentation.
For engineers reviewing the ADS1288IRHBR datasheet, ADS1288IRHBR pinout, ADS1288IRHBR application, or ADS1288IRHBR equivalent, this page provides verified technical context, real-world seismic use cases, validated pin functions, and confirmed alternative options for low-noise, high-resolution seismic ADC selection.
Technical Context
The ADS1288IRHBR implements a high-resolution delta-sigma modulator followed by a programmable FIR filter with selectable linear or minimum-phase response and integrated high-pass filtering to remove DC and low-frequency drift. Its sample rate converter compensates for clock frequency errors across –244ppm to +244ppm, enabling precise timing synchronization in distributed sensor arrays.
It integrates a two-channel analog multiplexer, offset/gain calibration registers, SYNC input for external timing alignment, and general-purpose digital I/Os (GPIO0/GPIO1). The PGA supports gains of 1–64 with 20nV/√Hz input voltage noise density (gain = 16), while the unity-gain buffer mode reduces power to 3mW typical-critical for extended battery life in remote seismic monitoring.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 32-bit output word length; enables sub-microvolt resolution in seismic signal capture over full-scale ranges. |
| Data Rate | 125–2000 SPS; supports high-fidelity sampling of seismic waveforms up to ~830 Hz bandwidth (0.413 × fDATA). |
| Dynamic Range | 122 dB (typical at 500 SPS); allows detection of weak seismic signals buried beneath thermal and environmental noise floors. |
| THD | < –120 dB (typical); ensures minimal harmonic distortion when digitizing low-amplitude, low-frequency earth motion signals. |
| CMRR | 120 dB (typical at 60 Hz); rejects common-mode interference from long cable runs in geophysical sensor deployments. |
| Power Consumption | 5 mW (PGA mode, 3.3V), 3 mW (buffer mode, 3.3V); enables multi-day operation on single lithium-thionyl chloride cells. |
| Clock Error Compensation | ±244 ppm range, 7.45 ppb resolution; maintains accurate sample timing without requiring ultra-stable crystal oscillators. |
Pinout & Package
The ADS1288IRHBR is housed in a 32-pin VQFN package (RHB), 5mm × 5mm, with exposed thermal pad connected to AVSS. Pin functions are validated per TI SBASAW0A (Nov 2025) datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1P / AIN1N AIN2P / AIN2N |
Differential analog inputs | Accepts direct connection to geophone or transformer-coupled hydrophone outputs; supports ±VREF/gain full-scale range. |
| CAPP / CAPN CAPBP / CAPBN |
Internal PGA/buffer capacitor terminals | Require external C0G capacitors (10nF and 47nF respectively) to stabilize internal amplifier bias networks. |
| REFP / REFN | Reference voltage inputs | Accept 2.4–2.6 V differential reference; reference current is 80 µA/V, enabling precision ratiometric measurement. |
| DIN / DOUT / SCLK / CS / DRDY | SPI-compatible serial interface | Supports standard 4-wire SPI with data-ready flag; DRDY falling edge indicates valid conversion result ready for readout. |
| SYNC / RESET / PWDN | Digital control inputs | SYNC enables synchronized sampling across multiple ADCs; RESET and PWDN provide hardware-level initialization and ultra-low-power sleep (1–5 µA). |
| GPIO0 / GPIO1 | General-purpose digital I/Os | Configurable as inputs or outputs via register control; usable for status signaling, sensor enable, or external trigger coordination. |
Key Features
| Feature | Design Value |
|---|---|
| Flexible digital filter architecture | Selectable sinc + FIR + IIR stages with linear or minimum-phase FIR response and programmable high-pass corner (0.1–10 Hz) for baseline wander removal. |
| Two-channel multiplexer | Enables sequential sampling of two independent seismic sensors (e.g., vertical + horizontal geophones) without external switching circuitry. |
| On-chip offset and gain calibration | Reduces system-level calibration effort; corrects up to ±6% FSR total error (offset + gain) via internal registers. |
| Analog supply flexibility | Operates from ±2.5V, 3.3V, or 5V AVDD1/AVSS rails-supports legacy industrial supplies and modern low-voltage battery systems. |
| Low-noise PGA (1–64 gain) | Extends effective resolution for microvolt-level geophone outputs; 20 nV/√Hz input noise at gain = 16 preserves SNR in weak-signal conditions. |
Applications
| Energy Exploration | Passive Seismic Monitoring |
|---|---|
|
Use Scenario: Deployed in land-based or marine node arrays to record reflected seismic waves from controlled sources (e.g., vibroseis trucks or airguns). IC Role / Device Role / Timing Role: Primary digitizer for geophone/hydrophone channels; provides synchronized, low-drift sampling with clock error compensation for time-of-flight analysis. Use Value: 122 dB dynamic range resolves both strong near-field reflections and weak deep-layer returns within same acquisition window. |
Use Scenario: Installed in boreholes or surface arrays to detect natural microseismic events (e.g., fracking-induced tremors or tectonic strain release). IC Role / Device Role / Timing Role: High-precision ADC front-end for ultra-low-power autonomous sensors; operates continuously for months on primary batteries. Use Value: 3 mW buffer-mode power consumption extends field deployment duration without compromising 122 dB signal fidelity. |
| Earth Sciences & Geology | Precision Instrumentation |
|
Use Scenario: Integrated into portable gravimeters, tiltmeters, and broadband seismometers used for crustal deformation studies and volcanic monitoring. IC Role / Device Role / Timing Role: Core analog front-end for DC-coupled, low-drift measurements; high CMRR (120 dB) rejects ground loop and EMI interference. Use Value: 0.5 µV/°C offset drift (PGA mode) ensures stable baseline over wide ambient temperature swings (–40°C to +85°C). |
Use Scenario: Used in laboratory-grade vibration analyzers, structural health monitoring systems, and calibration reference standards. IC Role / Device Role / Timing Role: Metrology-grade ADC with calibrated gain/offset registers and 7.45 ppb clock compensation for traceable time-domain accuracy. Use Value: <–120 dB THD and 115 dB SFDR enable distortion-free spectral analysis of mechanical resonance signatures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-resolution seismic ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS1287IRHBR | 32-bit, single-channel variant; identical noise performance (122 dB), but lacks second analog input and multiplexer. | Not suitable for dual-sensor simultaneous sampling; requires external mux for multi-channel systems. | Select when only one seismic channel is needed and board space or cost optimization is critical. |
| AD7768-1ACPZ | 24-bit, 256 kSPS sigma-delta ADC; higher speed but lower resolution; no integrated PGA or clock error compensation. | Better for high-bandwidth vibration analysis (>1 kHz), not optimized for sub-Hz seismic signal integrity or battery longevity. | Choose for wideband instrumentation where speed outweighs ultra-low-noise, low-power seismic requirements. |
Compared with ADS1287IRHBR and AD7768-1ACPZ, the ADS1288IRHBR uniquely combines dual-channel input, on-chip PGA, 32-bit resolution, and 7.45 ppb clock compensation-making it the only option qualified for autonomous, multi-node, battery-powered seismic arrays demanding both precision and timing coherence.
Availability
ADS1288IRHBR is available at Aetrix Electronics and suitable for energy exploration, passive seismic monitoring, and earth sciences instrumentation requiring stable component supply, long-term lifecycle support, and guaranteed traceability.
Supply support for ADS1288IRHBR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in precision data converters and industrial signal chain solutions.
The ADS1288IRHBR belongs to TI's high-precision delta-sigma ADC product line, engineered specifically for geophysical sensing applications where ultra-low noise, long-term stability, and low power consumption are non-negotiable.
FAQ
What is the maximum data rate supported by the ADS1288IRHBR?
The ADS1288IRHBR supports data rates from 125 SPS to 2000 SPS. At 2000 SPS, its –3 dB bandwidth is approximately 826 Hz (0.413 × fDATA), making it suitable for broadband seismic monitoring while retaining 116 dB dynamic range. Higher rates trade resolution for bandwidth, as oversampling ratio decreases.
Does the ADS1288IRHBR require external amplification for geophone signals?
No-the ADS1288IRHBR integrates a low-noise PGA with gains from 1 to 64, enabling direct connection to passive geophones and transformer-coupled hydrophones without external op-amps. Its input-referred noise of 20 nV/√Hz at gain = 16 preserves signal integrity for microvolt-level outputs.
How does the clock error compensation feature work in the ADS1288IRHBR?
The ADS1288IRHBR incorporates a sample rate converter that digitally adjusts output timing to compensate for input clock inaccuracies. It achieves ±244 ppm compensation range and 7.45 ppb resolution, allowing use of low-cost crystals while maintaining precise inter-node synchronization in distributed seismic arrays.
What are the recommended external capacitors for the ADS1288IRHBR PGA section?
The ADS1288IRHBR requires a 10 nF C0G capacitor between CAPP and CAPN pins, and a 47 nF C0G capacitor from CAPBP to AVSS. These stabilize internal bias networks; using X7R or NP0 alternatives may degrade THD and noise performance per TI SBASAW0A specifications.
Is the ADS1288IRHBR specified for operation across the full industrial temperature range?
Yes-the ADS1288IRHBR is fully specified from –40°C to +85°C ambient temperature. Key parameters including offset drift (0.5 µV/°C PGA mode), gain drift (2 ppm/°C), and CMRR (104–120 dB) are guaranteed across this range, ensuring reliability in outdoor seismic deployments.
ADS1288IRHBR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 32
- Sampling Rate (Per Second):
- 2k
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- SPI
- Configuration:
- MUX-PGA-ADC
- Ratio - S/H:ADC:
- 0:1
- Number of A/D Converters:
- 1
- Architecture:
- Sigma-Delta
- Reference Type:
- External
- Voltage - Supply, Analog:
- 2.375V ~ 5.25V
- Voltage - Supply, Digital:
- 1.65V ~ 3.6V
- Features:
- PGA
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-VQFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS1288IRHBR FAQ
1.How can I place an order for ADS1288IRHBR through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS1288IRHBR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS1288IRHBR reliable?
The price and inventory of ADS1288IRHBR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS1288IRHBR is usually 5 days.
3.What payment methods are accepted for ADS1288IRHBR?
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4.How is shipping managed for ADS1288IRHBR?
ADS1288IRHBR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS1288IRHBR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS1288IRHBR?
For technical support, including ADS1288IRHBR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS1288IRHBR requirements.
6.How does Aetrix verify that ADS1288IRHBR is sourced from the original manufacturer or authorized distributors?
All ADS1288IRHBR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS1288IRHBR meets industry standards.
7.What is the process for return or replacement of ADS1288IRHBR?
All ADS1288IRHBR units undergo pre-shipment inspection (PSI). If there is an issue with ADS1288IRHBR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS1288IRHBR part is unused and in its original packaging.
Return procedure for ADS1288IRHBR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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