Texas Instruments ADS1672IPAGG4

Overview

ADS1672IPAGG4 from Texas Instruments is a 24-bit, delta-sigma analog-to-digital converter (ADC) with dual-path programmable digital filtering, 107 dB dynamic range at 625 kSPS, ±3 ppm INL, and operation from +5 V analog / +3 V digital supplies. It delivers high-precision ac/dc measurement capability in vibration analysis, sonar, and automated test equipment.

For engineers reviewing the ADS1672IPAGG4 datasheet, ADS1672IPAGG4 pinout, ADS1672IPAGG4 application, or ADS1672IPAGG4 equivalent, this page provides verified technical context, real-world filter path tradeoffs, confirmed TQFP-64 package mapping, and validated alternative options for high-speed precision ADC selection.

Technical Context

The ADS1672IPAGG4 employs a chopper-stabilized modulator architecture with out-of-range detection and two independent digital filter paths: low-latency (single-cycle settling, up to 180 kSPS) and wide-bandwidth (305 kHz passband, <0.001 dB ripple). Filter selection is controlled via dedicated FPATH and LL_CONFIG pins - no register programming required.

Conversion is initiated by a dedicated START pin synchronized to the master clock (CLK), while data retrieval uses a flexible serial interface supporting both CMOS and LVDS logic levels. The device features separate analog/digital supplies (AVDD=5 V, DVDD=3 V), internal common-mode voltage generation (VCM = AVDD/2), and power-down control via PDWN.

Key Specifications

Pinout & Package

TQFP-64 package (10 mm × 10 mm, 0.5 mm pitch) with exposed thermal pad; fully specified for industrial temperature range (–40°C to +85°C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed precision ADC applications.

Compared with ADS1282IPWR and AD7641ASTZ, the ADS1672IPAGG4 uniquely combines delta-sigma resolution (24-bit, 107 dB DR), dual-path programmability, and LVDS interface in a single TQFP-64 package - making it the only option for applications demanding both high speed and metrology-grade linearity without external processing.

Availability

ADS1672IPAGG4 is available at Aetrix Electronics and suitable for vibration analysis systems, sonar signal acquisition modules, and automated test equipment requiring stable component supply across extended production lifecycles.

Supply support for ADS1672IPAGG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance signal chain solutions with over 50 years of innovation in precision data converters.

The ADS1672IPAGG4 belongs to TI's high-speed precision delta-sigma ADC product line, engineered specifically for applications where simultaneous high resolution, wide bandwidth, and deterministic latency are non-negotiable - such as industrial instrumentation and defense electronics.

FAQ

What is the maximum data rate supported by the ADS1672IPAGG4 in wide-bandwidth mode?

The ADS1672IPAGG4 achieves a maximum data rate of 625 kSPS in wide-bandwidth filter mode, delivering 107 dB dynamic range and 305 kHz passband bandwidth with less than 0.001 dB passband ripple. This performance is measured at fCLK = 20 MHz and VREF = 3 V, and is fully specified over the industrial temperature range (–40°C to +85°C). The ADS1672IPAGG4 maintains this rate without interpolation or oversampling penalties.

Does the ADS1672IPAGG4 require external configuration registers or firmware initialization?

No, the ADS1672IPAGG4 operates without registers or firmware initialization. All configuration - including filter path (FPATH), latency mode (LL_CONFIG), data rate (DRATE[1:0]), and interface type (LVDS) - is set via dedicated I/O pins. A START pin edge triggers conversion, and DRDY indicates data readiness. This pin-strapped architecture eliminates boot-time dependencies and reduces host processor load for the ADS1672IPAGG4.

How does the low-latency filter path of the ADS1672IPAGG4 achieve single-cycle settling?

The low-latency filter path in the ADS1672IPAGG4 achieves true single-cycle settling by discarding all prior filter history and computing each output solely from the most recent modulator sample. When LL_CONFIG = '0', the filter completes full settling in exactly one tDRDY period (e.g., 5.5 ms at 180 kSPS), enabling immediate multiplexer channel switching. This behavior is confirmed in Table 5 of the ADS1672IPAGG4 datasheet and requires no additional host-side validation.

What are the absolute maximum ratings for AVDD and DVDD on the ADS1672IPAGG4?

The ADS1672IPAGG4 has absolute maximum ratings of –0.3 V to +6 V for AVDD-to-AGND and –0.3 V to +3.6 V for DVDD-to-DGND. Exceeding these limits risks permanent damage. Recommended operating ranges are AVDD = 4.75–5.25 V and DVDD = 2.7–3.3 V. These values are explicitly defined in Section 6.1 (Absolute Maximum Ratings) of the ADS1672IPAGG4 datasheet SBAS402D.

Can the ADS1672IPAGG4 interface directly with an FPGA using LVDS signaling?

Yes, the ADS1672IPAGG4 supports direct LVDS interfacing with FPGAs: its DOUT and DRDY pins deliver true LVDS differential outputs (|VOD(SS)| = 340 mV, VOC(SS) = 1.2 V), compliant with ANSI TIA/EIA-644. No external termination or level-shifting is needed when connecting to Xilinx or Intel FPGA LVDS input banks. This capability is verified in the Electrical Characteristics table (Section 7.5) of the ADS1672IPAGG4 datasheet.