Texas Instruments ADS1672IPAGR

Overview

ADS1672IPAGR from Texas Instruments is a 24-bit, delta-sigma analog-to-digital converter (ADC) with dual-path programmable digital filtering, 107 dB dynamic range at 625 kSPS, ±3 ppm INL, and chopper-stabilized modulator architecture. It operates from +5 V analog and +3 V digital supplies, dissipates 350 mW, and targets high-precision ac/dc measurement in vibration analysis and sonar systems.

For engineers reviewing the ADS1672IPAGR datasheet, ADS1672IPAGR pinout, ADS1672IPAGR application, or ADS1672IPAGR equivalent, this page delivers verified technical context, TQFP-64 package mapping, low-latency/wide-bandwidth filter tradeoffs, out-of-range detection behavior, and CMOS/LVDS serial interface timing constraints - all confirmed against SBAS402D Rev. D (2010).

Technical Context

The ADS1672IPAGR integrates a chopper-stabilized delta-sigma modulator with out-of-range detection and two independent digital filter paths: low-latency (single-cycle settling, 5.5 ms full settle at 180 kSPS) and wide-bandwidth (305 kHz passband, <0.001 dB ripple, 86 dB stopband attenuation). Filter selection is controlled via dedicated FPATH and LL_CONFIG pins - no register programming required.

Conversion is initiated by toggling the START pin synchronized to the master clock (CLK); data retrieval uses DRDY-strobed SCLK (internally or externally generated) with configurable CMOS or LVDS output levels. The device supports differential input (AINP/AINN), external reference (VREFP/VREFN), and common-mode bias (VCM) for precision signal conditioning.

Key Specifications

Pinout & Package

TQFP-64 package (10 mm × 10 mm, 0.5 mm pitch) with exposed thermal pad; lead-free and RoHS-compliant per TI specifications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed, high-precision delta-sigma ADC applications.

Compared with ADS1672IPAGR, ADS1675IPAG extends bandwidth and speed at higher power, while AD7768-1ACPZ trades configurability and settling speed for integration and efficiency - making ADS1672IPAGR the optimal balance for industrial ATE and sonar where deterministic latency and no-register control are mandatory.

Availability

ADS1672IPAGR is available at Aetrix Electronics and suitable for automated test equipment, vibration analysis systems, sonar signal acquisition, and high-precision test & measurement requiring stable component supply across long production lifecycles.

Supply support for ADS1672IPAGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADS1672IPAGR belongs to TI's precision delta-sigma ADC product line, engineered for applications demanding simultaneous high resolution, wide bandwidth, and deterministic latency - such as real-time structural health monitoring and acoustic beamforming.

FAQ

What is the maximum data rate supported by ADS1672IPAGR?

The ADS1672IPAGR supports up to 625 kSPS in wide-bandwidth filter mode and 180 kSPS in low-latency mode with single-cycle settling. These rates are set by DRATE[1:0] pins and are fully characterized across –40°C to +85°C. At 625 kSPS, dynamic range is 107 dB; at 78.125 kSPS, it improves to 115.5 dB. The ADS1672IPAGR does not support rates beyond 625 kSPS.

Does ADS1672IPAGR require external registers or SPI configuration?

No. The ADS1672IPAGR uses pin-strapped configuration: FPATH, LL_CONFIG, DRATE[1:0], LVDS, and SCLK_SEL pins directly control filter path, data rate, interface type, and clock source - eliminating SPI/I²C initialization. This design makes ADS1672IPAGR ideal for FPGA-based systems where deterministic startup and minimal firmware overhead are critical.

How does the low-latency filter in ADS1672IPAGR achieve single-cycle settling?

The low-latency filter in ADS1672IPAGR achieves single-cycle settling by using a simplified decimation structure that outputs valid data after exactly one conversion cycle - no discarded samples required. When LL_CONFIG = 0 and FPATH = 1, the ADS1672IPAGR guarantees complete settling in 5.5 ms at 180 kSPS, enabling rapid multiplexer scanning without dead time between channels.

What is the role of the OTRD pin on ADS1672IPAGR?

The OTRD (Out-of-Range Detection) pin on ADS1672IPAGR is an open-drain digital output that asserts low when the differential input (AINP – AINN) exceeds ±VREF. It operates independently of the digital filter path and provides real-time fault indication without host processor polling - critical for protecting downstream signal chains in automated test equipment and sonar receivers.

Can ADS1672IPAGR operate with a 2.5 V reference voltage?

No. ADS1672IPAGR specifies VREF = (VREFP – VREFN) between 2.75 V and 3.25 V per the datasheet (SBAS402D, Section "Voltage Reference Inputs"). Operation outside this range risks degraded INL, reduced dynamic range, and noncompliance with AC/DC specifications. For 2.5 V reference systems, external scaling or a different ADC such as ADS127L01 must be considered - ADS1672IPAGR requires ≥2.75 V reference.