Texas Instruments ADS1675IPAG

Overview

ADS1675IPAG from Texas Instruments is a 24-bit delta-sigma analog-to-digital converter (ADC) with dual-path digital filtering, 4MSPS maximum data rate, 103dB dynamic range at full speed, –107dB THD, and ±3ppm INL. It operates from +5V analog and +3V digital supplies, dissipates 575mW, and targets high-precision acquisition in automated test equipment and medical imaging systems.

For engineers reviewing the ADS1675IPAG datasheet, ADS1675IPAG pinout, ADS1675IPAG application, or ADS1675IPAG equivalent, key selection considerations include filter path selection (Low-Latency vs Wide-Bandwidth), LVDS/CMOS interface compatibility, out-of-range detection capability, START-pin conversion control, and TQFP-64 package thermal and layout constraints.

Technical Context

The ADS1675IPAG integrates a low-drift delta-sigma modulator with out-of-range detection and a user-selectable dual-path digital filter: Low-Latency path settles in 2.65ms for multiplexed or transient-heavy inputs, while Wide-Bandwidth path delivers 1.7MHz bandwidth, ±0.00002dB passband ripple, and 86dB stopband attenuation. It supports two speed modes-high-speed (DRATE = 100/101, up to 4MSPS, 23-bit resolution) and low-speed (DRATE = 000–011, down to 125kSPS, 24-bit resolution).

Control is implemented via dedicated I/O pins-no register programming required. The START pin initiates conversion and synchronization; FPATH selects filter path; DRATE[2:0] configures data rate; LVDS pin toggles CMOS/LVDS interface mode; SCLK_SEL determines internal or external serial clock sourcing. PLL-based clocking ensures stable 32MHz master clock operation with 80ms settling time.

Key Specifications

Pinout & Package

TQFP-64 package with 0.5mm pitch, 10mm × 10mm body, exposed thermal pad (not electrically connected), and industrial temperature range (–40°C to +85°C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed, high-precision ADC applications.

Compared with ADS1282IPWR and AD7641ASTZ, the ADS1675IPAG uniquely combines 4MSPS delta-sigma performance, dual-path filtering, and LVDS/CMOS interface flexibility-making it optimal for high-fidelity, high-throughput acquisition where both speed and precision are non-negotiable.

Availability

ADS1675IPAG is available at Aetrix Electronics and suitable for automated test equipment, medical imaging subsystems, scientific instrumentation, and high-accuracy data acquisition systems requiring stable component supply across extended production lifecycles.

Supply support for ADS1675IPAG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in precision data converters and industrial-grade IC design.

The ADS1675IPAG belongs to TI's high-performance delta-sigma ADC product line, engineered specifically for applications demanding simultaneous high resolution, wide dynamic range, and flexible digital filtering-such as next-generation ATE, diagnostic imaging, and metrology-grade instrumentation.

FAQ

What is the maximum data rate supported by the ADS1675IPAG?

The ADS1675IPAG supports a maximum data rate of 4MSPS in high-speed mode (DRATE = 101). At this rate, resolution is 23 bits, dynamic range is 103dB, and THD is –107dB. Lower data rates (down to 125kSPS) enable 24-bit resolution and improved noise performance, as confirmed in the SBAS416D datasheet Table 1.

Does the ADS1675IPAG require external configuration registers?

No, the ADS1675IPAG uses pin-strapped configuration-no internal registers or SPI/I²C programming is required. All operating parameters-including data rate (DRATE[2:0]), filter path (FPATH), interface type (LVDS), and clock source (SCLK_SEL)-are set directly via dedicated digital I/O pins, simplifying firmware integration and reducing boot-time dependencies.

How does the Low-Latency filter path differ from the Wide-Bandwidth path in the ADS1675IPAG?

The Low-Latency path achieves complete digital filter settling in 2.65ms, making it ideal for multiplexed inputs or rapidly changing signals. The Wide-Bandwidth path offers 1.7MHz bandwidth, ±0.00002dB passband ripple, and 86dB stopband attenuation-optimized for high-fidelity ac measurements. Both paths are selected dynamically via the FPATH pin on the ADS1675IPAG.

What are the supply voltage requirements for the ADS1675IPAG?

The ADS1675IPAG requires two independent supplies: AVDD = +4.75V to +5.25V (analog domain) and DVDD = +2.85V to +3.15V (digital domain). These must be separately decoupled; AGND and DGND are internally isolated but must be connected at a single point on the PCB to minimize ground bounce and maintain PSRR integrity in the ADS1675IPAG.

Can the ADS1675IPAG interface directly with an FPGA using LVDS signaling?

Yes, the ADS1675IPAG provides native differential LVDS outputs for DRDY and DOUT signals, supporting direct connection to FPGA LVDS input banks without level shifters. The LVDS interface is enabled by setting the LVDS pin low; timing parameters-including tLDOPD (1.5–2.5ns propagation delay) and SCLK duty cycle (47–53%)-are fully specified for FPGA synchronization in the ADS1675IPAG datasheet.