Texas Instruments ADS4128IRGZT

Overview

ADS4128IRGZT from Texas Instruments is a 12-bit, 200-MSPS analog-to-digital converter (ADC) optimized for wideband communications signal acquisition. It delivers 69 dBFS SNR at 170 MHz input, consumes only 230 mW at full rate on a single 1.8-V supply, and supports DDR LVDS output with programmable 200/350-mV swing in a 7.00 mm × 7.00 mm VQFN-48 package. It is deployed in multi-carrier base station receivers requiring high dynamic range and ultralow power.

For engineers reviewing the ADS4128IRGZT datasheet, ADS4128IRGZT pinout, ADS4128IRGZT application, or ADS4128IRGZT equivalent, key selection criteria include its 200-MSPS sampling capability, LVDS/CMOS dual-output flexibility, DC offset correction loop, fine-gain programmability up to 6 dB, and industrial-temperature operation (–40°C to 85°C).

Technical Context

The ADS4128IRGZT employs a pipeline ADC architecture with integrated input buffer, on-chip reference, and digital calibration logic. Its differential analog input supports up to 400 MHz bandwidth with 2-V_PP full-scale range and 0.95-V common-mode output (VCM) for external biasing.

Dual-mode digital interface supports either DDR LVDS (with 100-Ω or 50-Ω termination options) or parallel 12-bit CMOS outputs. Clocking includes differential CLKP/CLKM inputs accepting as low as 200 mV_PP, plus programmable CLKOUTP/CLKOUTM or CLKOUT for synchronization.

Key Specifications

Pinout & Package

VQFN-48 package (7.00 mm × 7.00 mm) with exposed thermal pad connected to DRGND. Pin functions support both LVDS and CMOS output modes, with dedicated analog/digital supply and ground separation for noise isolation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS4128IRGZT, ADS4149IRGZT trades power efficiency for resolution headroom, while AD9230BCPZ-200 replaces parallel LVDS/CMOS with serial JESD204B-requiring different FPGA IP and layout strategy but enabling higher channel density.

Availability

ADS4128IRGZT is available at Aetrix Electronics and suitable for wireless infrastructure, software-defined radio, and power amplifier linearization applications requiring stable component supply, long-term industrial temperature support, and production-ready LVDS/CMOS interface compatibility.

Supply support for ADS4128IRGZT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADS41xx family targets wideband communications systems where ultralow power, high dynamic range, and flexible digital interfacing are essential-designed specifically for base station, SDR, and test equipment signal chains.

FAQ

What is the maximum analog input frequency supported by the ADS4128IRGZT?

The ADS4128IRGZT supports analog input frequencies up to 400 MHz with a 2-V_PP input amplitude and up to 800 MHz with a 1-V_PP amplitude, enabled by its 550-MHz analog input bandwidth. This allows direct sampling of IF signals in cellular infrastructure and radar applications without additional downconversion stages. The device maintains specified SNR and SFDR performance within these ranges per its electrical characteristics table.

Does the ADS4128IRGZT support both LVDS and CMOS output interfaces simultaneously?

No, the ADS4128IRGZT does not support simultaneous LVDS and CMOS outputs. Interface selection is controlled by the DFS pin at power-up: LVDS mode activates DDR multiplexed differential outputs (e.g., D0_D1P/D0_D1M), while CMOS mode enables 12 individual single-ended outputs (D0–D11). The ADS4128IRGZT must be configured for one interface type per power cycle; reconfiguration requires hardware reset or register programming.

How does the DC offset correction feature operate in the ADS4128IRGZT?

The ADS4128IRGZT includes a hardware-based DC offset correction loop that continuously measures and subtracts input-referred offset in real time. It operates automatically upon power-up and remains active unless disabled via register control. The correction improves baseline stability for DC-coupled applications like DPD feedback paths, eliminating drift-induced errors without external calibration circuitry. Offset error is specified as ±15 mV over temperature.

What is the latency of the ADS4128IRGZT in low-latency mode?

In low-latency mode (default after reset), the ADS4128IRGZT exhibits 10 clock cycles of latency from input sample to valid output data. This deterministic delay is critical for closed-loop systems such as digital predistortion, where timing alignment between transmit and receive paths must be tightly controlled. Latency increases to 16 or 17 cycles when fine-gain or DC offset correction are enabled, as documented in the timing requirements section.

Can the ADS4128IRGZT operate with a single-ended clock input?

No, the ADS4128IRGZT requires a differential clock input on CLKP and CLKM pins. It does not support single-ended clocking. However, it accepts low-amplitude differential inputs down to 200 mV_PP and is compatible with LVDS, LVPECL, and ac-coupled sine-wave clock sources. Single-ended clocks must be converted to differential using a balun or dedicated clock buffer before connection to the ADS4128IRGZT.