Texas Instruments ADS5287IRGCT

Overview

ADS5287IRGCT from Texas Instruments is a 10-bit, octal-channel analog-to-digital converter (ADC) with serialized LVDS outputs, integrated PLL clock buffer, and programmable digital gain (0–12 dB). It operates up to 65 MSPS, delivers 61.7 dBFS SNR at 10 MHz IF, supports 2 V_PP differential analog input, and targets high-density data acquisition in medical imaging and wireless infrastructure.

For engineers reviewing the ADS5287IRGCT datasheet, ADS5287IRGCT pinout, ADS5287IRGCT application, or ADS5287IRGCT equivalent, key selection factors include its 64-pin QFN package, dual LVDS clock outputs (1× and 6×), channel-specific power-down control, internal/external reference flexibility, and low-frequency noise suppression mode.

Technical Context

The ADS5287IRGCT integrates eight independent 10-bit ADC cores sharing a single high-stability PLL-based clock buffer that generates both frame clock (ADCLKP/ADCLKN at sample rate) and bit clock (LCLKP/LCLKN at 6× sample rate). Each channel features configurable digital gain, polarity inversion, and low-noise mode via serial register interface.

Its serialized DDR LVDS output architecture reduces interconnect count versus parallel interfaces, while programmable drive current (3.5 mA default), internal termination enable, and per-channel power-down support system-level power optimization across sampling rates from 10 to 65 MSPS.

Key Specifications

Pinout & Package

ADS5287IRGCT is housed in a thermally enhanced 9 mm × 9 mm QFN-64 PowerPAD™ package with exposed thermal pad (pin 35 = LVDD, pins 12/14/36 = LVSS, pins 3/6/9/37/40/43/46 = AVSS).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar octal ADC applications.

Compared with ADS5287IRGCT, ADS5282IRGCT offers higher resolution at increased power cost, while ADS5272IRGCT provides direct 12-bit pin-compatible replacement-both retain identical LVDS serialization, register map, and power-down architecture for seamless integration.

Availability

ADS5287IRGCT is available at Aetrix Electronics and suitable for medical ultrasound imaging, wireless base station infrastructure, and automated test equipment requiring stable component supply across extended product lifecycles.

Supply support for ADS5287IRGCT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADS5287IRGCT belongs to TI's high-speed octal ADC family designed for space-constrained, multi-channel digitization systems demanding low power, serialized outputs, and flexible reference architecture.

FAQ

What is the maximum sampling rate supported by the ADS5287IRGCT?

The ADS5287IRGCT supports a maximum sampling rate of 65 MSPS across all eight channels simultaneously. This rate is validated over the full industrial temperature range (–40°C to +85°C) with AVDD = 3.3 V and LVDD = 1.8 V. At 65 MSPS, the device consumes 719.1 mW total power and achieves 61.7 dBFS SNR at 10 MHz input frequency. Lower rates (e.g., 30 MSPS) reduce power to 46 mW per channel while maintaining full 10-bit performance.

Does the ADS5287IRGCT support both internal and external reference modes?

Yes, the ADS5287IRGCT supports both internal and external reference configurations. In internal mode, it uses a trimmed 2.0 V reference (VREFT – VREFB = 2.0 V ±25 mV). In external mode, it accepts 0.5 V on REFB and 2.5 V on REFT, enabling higher precision when paired with a low-drift external reference. The INT/EXT pin selects mode at power-up, and register settings can override this during operation. Reference loading is specified at 3.5 mA total switching current.

How does the LVDS serialization work on the ADS5287IRGCT?

The ADS5287IRGCT uses DDR LVDS serialization: each 10-bit sample is transmitted across two consecutive LCLK cycles (6× sample rate), reducing pin count versus parallel interfaces. Eight channels produce eight differential LVDS pairs (OUT1P/OUT1N through OUT8P/OUT8N), each carrying time-multiplexed data. Frame clock (ADCLKP/ADCLKN) marks sample boundaries, while bit clock (LCLKP/LCLKN) times individual bits. Total latency is fixed at 12 clock cycles from analog input to first valid data.

What power-down modes are available on the ADS5287IRGCT?

The ADS5287IRGCT offers three power-down configurations: complete power-down (45 mW, wake-up <50 μs), partial power-down (135 mW with clock active, wake-up <2 μs), and per-channel power-down (61 mW saved per disabled channel). These are controlled via hardware PD pin or serial register bits (PDN_CH<8:1>, PDN_PARTIAL, PDN_COMPLETE). Partial mode retains clock distribution for fast resumption, while complete mode shuts down all analog and digital blocks except reset logic.

Can the ADS5287IRGCT generate test patterns for interface validation?

Yes, the ADS5287IRGCT includes on-chip test pattern generation accessible via serial registers. It supports a repeating full-scale ramp (EN_RAMP), dual custom codes (DUALCUSTOM_PAT), or single constant code (SINGLE_CUSTOM_PAT), all output via LVDS. These patterns eliminate need for external signal sources during FPGA interface bring-up, JESD204B link testing, or board-level functional verification. Pattern selection and values are programmed through registers 0x24–0x27 with no analog input required.