Texas Instruments ADS52J90EVM

Overview

ADS52J90EVM from Texas Instruments is an evaluation module designed to characterize the ADS52J90 8/16/32-channel, 14-bit analog-to-digital converter (ADC) under real-world signal, clock, reference, and output interface conditions. It supports both LVDS and JESD204B serial data interfaces, features on-board LMK04826 clock distribution, configurable analog input modes (8/16/32-ch), and integrates with TSW1400 (LVDS) or TSW14J56 (JESD204B) capture cards for data analysis.

For engineers reviewing the ADS52J90EVM datasheet, ADS52J90EVM pinout, ADS52J90EVM application, or ADS52J90EVM equivalent, this page provides verified hardware configuration details, interface-specific setup requirements, GUI software dependencies (HSDCpro v3.1+, HMC-DAQ), clocking constraints for deterministic latency, and test point access for analog/digital power and SPI control signals.

Technical Context

The ADS52J90EVM implements a dual-interface ADC evaluation architecture: one path routes LVDS outputs to the TSW1400 de-serializer board via high-speed connector J44, while the other routes JESD204B lanes to the TSW14J56 board. Clocking is centralized through the LMK04826 (U2), configured in Clock Distribution Mode (CDM) to derive device clock (Fs), SYSREF, and FPGA GTX clocks from a single SMA reference input (J75).

Hardware configurability is achieved via 2–3-pin jumpers (JP2–JP41, JP700_7, JP800_8) that select power domains (+1.2V DVDD, +1.8V AVDD/LVDD), SYNC sources (SMA/FPGA/GUI), clock routing (auxiliary XTALs or LMK outputs), and analog channel mode (8/16/32-ch). Test points provide direct access to all critical power rails, SPI lines, reset controls, and differential clock/SYSREF signals.

Key Specifications

Availability

ADS52J90EVM is available at Aetrix Electronics and suitable for high-speed data acquisition system validation, JESD204B protocol verification, multi-channel ADC performance benchmarking, and clock distribution architecture testing requiring stable component supply and full technical documentation support.

Supply support for ADS52J90EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and high-speed data converter technologies.

The ADS52J90EVM belongs to TI's High-Speed Data Converter Evaluation Platform family, engineered to accelerate development of multi-channel, high-resolution ADC systems used in medical imaging, communications infrastructure, and test equipment.

FAQ

What is the primary function of the ADS52J90EVM?

The ADS52J90EVM is a dedicated evaluation platform for the ADS52J90 8/16/32-channel, 14-bit analog-to-digital converter. It enables engineers to validate ADC performance-including SNR, ENOB, and channel matching-under configurable LVDS or JESD204B output formats, variable clocking schemes, and multiple analog input channel configurations. The ADS52J90EVM itself contains no ADC silicon; it hosts the ADS52J90 device and provides all necessary signal conditioning, clock generation, power regulation, and interface connectivity.

Which capture cards are required to use the ADS52J90EVM?

The ADS52J90EVM requires either the TSW1400 EVM for LVDS interface evaluation or the TSW14J56 EVM for JESD204B interface evaluation-only one capture card may be used at a time. Both cards connect via high-speed edge connector J44 and communicate with the PC via USB. The ADS52J90EVM does not include either capture card; they must be ordered separately. Each card runs the same HSDCpro GUI but loads different FPGA firmware specific to the interface protocol.

Does the ADS52J90EVM include the ADS52J90 ADC IC?

Yes, the ADS52J90EVM includes the ADS52J90 integrated circuit mounted on the board. The module is built around the ADS52J90 device and provides full access to its analog inputs, digital outputs, SPI control interface, power supplies, and synchronization pins. All jumper configurations, test points, and clock routing options described in the SLAU632B User's Guide apply directly to the ADS52J90 IC hosted on the ADS52J90EVM.

What clocking options does the ADS52J90EVM support for the ADS52J90 device?

The ADS52J90EVM supports multiple clocking configurations via the LMK04826 (U2). The ADS52J90 device clock (Fs) and SYSREF can be sourced from the LMK04826's outputs, from auxiliary SMA inputs (J55, J50), or from on-board oscillators (10 MHz XTAL1, 40 MHz XTAL2, 100 MHz OSC1). Jumpers JP39–JP41 and JP7–JP8 determine signal routing and source selection, enabling precise control over sampling clock phase noise, jitter, and deterministic latency alignment.

Can the ADS52J90EVM operate in 8-channel, 16-channel, and 32-channel modes simultaneously?

No, the ADS52J90EVM supports only one analog input channel mode at a time-8-channel, 16-channel, or 32-channel-selected via hardware jumpers JP700_7 and JP800_8 and confirmed by physical SMA connector usage. In 8-channel mode, only CH7 and CH8 are active with differential and single-ended input paths respectively; in 16-channel mode, odd-numbered channels (1, 3, ..., 23) are enabled; in 32-channel mode, all 24 SMA inputs (CH1–CH24) are used. The ADS52J90EVM does not support concurrent operation across multiple modes.