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Texas Instruments ADS5402IZAY
- Part No.:
- ADS5402IZAY
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 196-LFBGA
- Datasheet:
-
ADS5402IZAY.pdf
- Description:
- IC ADC 12BIT PIPELINED 196NFBGA
- Quantity:
- Payment:
- Shipping:
Inventory:1,766
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Product details
Overview
ADS5402IZAY from Texas Instruments is a dual-channel, 12-bit, 800 Msps analog-to-digital converter (ADC) with DDR LVDS digital output, >1.2 GHz analog input bandwidth, and integrated analog input buffer for high-impedance signal coupling in wideband receiver front ends. It supports optional 2× decimation with programmable FIR filtering and operates across –40°C to +85°C.
For engineers reviewing the ADS5402IZAY datasheet, ADS5402IZAY pinout, ADS5402IZAY application, or ADS5402IZAY equivalent, key selection criteria include its 800 Msps sampling rate, dual-channel interleaving correction, low 100 fs rms aperture jitter, 196-pin BGA package (12×12 mm), and support for synchronous multi-ADC systems via SYNCOUT and SYNC inputs.
Technical Context
The ADS5402IZAY implements a pipeline ADC architecture with on-chip track-and-hold, auto-calibration for offset/gain/interleaving errors, and dual independent digital blocks feeding separate DDR LVDS output buses (DA[11:0] and DB[11:0]). Clock distribution includes differential CLKIN with internal 0.9 V common-mode bias and programmable DACLKP/N and DBCLKP/N edges for data capture alignment.
It features configurable power modes (standby, light/deep sleep, shutdown), SPI-based register control (SCLK/SDIO/SDO/SDENB/SRESET), and real-time overrange detection per channel (OVRAP/N, OVRBP/N). The analog input stage accepts ±0.5 V differential signals (1.0 Vpp full-scale) with 1.9 V common-mode output (VCM) and 2.0 V reference (VREF).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Resolution | 12-bit - delivers 12-bit quantization precision with ≤±2 LSB DNL and ≤±5 LSB INL at 230 MHz input. |
| Sampling Rate | 800 Msps - supports Nyquist-limited IF sampling up to 400 MHz; enables direct RF sampling in microwave receivers. |
| Analog Input Bandwidth | >1.2 GHz (3 dB) - preserves signal integrity for ultra-wideband applications including radar and SDR. |
| Aperture Jitter | 100 fs rms - limits SNR degradation at high input frequencies; enables 61.3 dBFS SNR at 230 MHz. |
| Data Interface | DDR LVDS - reduces I/O count vs. single-data-rate; supports 1.6 Gbps per bus (DA/DB) with 250–450 mV differential swing. |
| Power Dissipation | 2.18 W typical (auto-correction enabled) - split across AVDD33 (350 mA), AVDD18 (120 mA), DVDD (400 mA), and DVDDLVDS (170 mA). |
| Operating Temperature | –40°C to +85°C - qualified for industrial and communications infrastructure environments without derating. |
| Package | 196-pin nFBGA (12×12 mm, 0.8 mm pitch) - supports high-density PCB layouts with thermal pad for junction-to-board θJB = 16.8°C/W. |
Pinout & Package
The ADS5402IZAY is housed in a 196-ball nFBGA package (ZAY designation) with exposed thermal pad, 0.8 mm ball pitch, and 12 mm × 12 mm footprint. Pin assignments follow JEDEC MO-276AA standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INA_P/N, INB_P/N | Differential analog inputs (Ch A/B) | High-impedance buffered inputs accepting 1.0 Vpp differential signals; internal 1.9 V common-mode bias (VCM). |
| CLKINP/N | Differential clock input | Accepts LVDS/LVPECL/sine sources; internally biased to 0.9 V; requires external 100 Ω termination near pins. |
| SYNCP/N | Synchronization input | Resets internal clocks and logic; enables deterministic multi-ADC alignment; 100 Ω internal termination. |
| DA[11:0]P/N, DB[11:0]P/N | DDR LVDS data outputs (Ch A/B) | 12-bit parallel DDR outputs; each pair provides 250–450 mV differential swing at 1.6 Gbps; require matched trace lengths. |
| DACLKP/N, DBCLKP/N | DDR data clock outputs | Programmable edge (rising/falling) to center data valid window; critical for timing closure in FPGA/ASIC interfaces. |
| OVRAP/N, OVRBP/N | Per-channel overrange indicators | LVDS-level flags signaling input exceeding ±0.5 V differential; enable real-time clipping detection without host processing. |
| VREF, VCM | Analog reference & common-mode outputs | VREF = 2.0 V nominal (0.1 μF to AGND); VCM = 1.9 V nominal (0.1 μF to AGND); used for external circuit biasing. |
| AVDD33, AVDD18, DVDD, DVDDLVDS | Supply rails | Separate 3.3 V (analog), 1.8 V (analog clock/digital/LVDS) supplies minimize noise coupling and enable domain-specific power sequencing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel interleaving correction | On-the-fly gain/offset/phase calibration eliminates mismatch spurs, enabling ≥74 dBc SFDR at 230 MHz without external tuning. |
| Optional 2× decimation filter | Configurable low-pass or high-pass FIR reduces output data rate to 400 Msps while preserving spectral integrity for baseband processing. |
| Synchronous multi-ADC operation | SYSNCIN/SYNCOUT interface allows deterministic phase alignment of up to 4 ADS5402IZAY devices for coherent wideband sampling. |
| Low-power operational modes | Light-sleep (2 µs wake-up, 820 mW) and deep-sleep (20 µs wake-up, 510 mW) support burst-mode acquisition in power-constrained systems. |
| Test pattern generation | Four built-in digital test patterns (all-0, all-1, toggle, custom) accessible via SPI registers x3C–x3E verify LVDS link integrity pre-deployment. |
| Robust clock input interface | Differential CLKIN with internal 2 kΩ bias resistors enables AC-coupled clock sources; minimizes sensitivity to external jitter and supply noise. |
Applications
| Radar and Satellite Systems | Ultra-Wide Band Software Defined Radio |
|---|---|
Use Scenario: Direct sampling of L/S-band radar IF signals (1–3 GHz) in phased-array receivers requiring high dynamic range and phase coherence across multiple channels. IC Role / Device Role / Timing Role: Dual-channel ADC digitizing two independent antenna paths with synchronized sampling and interleaving correction to suppress image spurs. Use Value: Enables 74 dBc SFDR at 230 MHz and 69 dBc at 700 MHz, meeting stringent clutter rejection requirements in pulse-Doppler radar. | Use Scenario: Wide instantaneous bandwidth capture in military/commercial SDR transceivers supporting multi-standard reconfiguration (LTE, WiMAX, 5G NR). IC Role / Device Role / Timing Role: Front-end ADC providing 1.2 GHz analog bandwidth and 800 Msps sampling to support ≥400 MHz instantaneous bandwidth per channel. Use Value: Delivers 61.3 dBFS SNR at 230 MHz and 59.8 dBFS at 700 MHz, ensuring high modulation accuracy for 256-QAM waveforms. |
| Signal Intelligence and Jamming | Microwave Receivers |
Use Scenario: Real-time spectrum monitoring and adaptive jamming in electronic warfare platforms operating across C/X bands (4–12 GHz). IC Role / Device Role / Timing Role: High-linearity ADC capturing wideband IF signals with overrange detection (OVRAP/N, OVRBP/N) for automatic gain control feedback. Use Value: 100 fs aperture jitter and >1.2 GHz bandwidth preserve transient fidelity for pulse analysis and chirp detection. | Use Scenario: Digitization of downconverted satellite TV or point-to-point backhaul signals in 26–40 GHz E-band receivers. IC Role / Device Role / Timing Role: Dual ADC supporting I/Q demodulation with independent channel calibration to maintain image rejection ratio (IRR) >70 dB. Use Value: Integrated analog input buffer isolates sensitive front-end filters from switching noise, easing anti-alias filter design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed dual-channel ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS5409IZAY | 900 Msps max sampling rate; identical 12-bit resolution, 196-BGA package, and DDR LVDS interface; higher power (2.7 W typical). | Supports wider Nyquist zones (up to 450 MHz IF); better suited for millimeter-wave IF sampling where higher clock rates reduce aliasing risk. | Select ADS5409IZAY when system clocking supports ≥900 MHz and SNR at >700 MHz is critical; verify thermal management for +0.5 W dissipation increase. |
| AD9689BCPZ-1300 | 14-bit, 1.3 GSPS; JESD204B serial interface (not LVDS); different pinout and power architecture; supports on-chip DDC and NCO. | Targets software-defined systems requiring digital downconversion and lower lane count; lacks native SYNCOUT for multi-chip synchronization without FPGA logic. | Choose AD9689BCPZ-1300 for JESD204B-based architectures needing spectral processing offload; avoid if LVDS compatibility or deterministic multi-ADC sync is required. |
Compared with ADS5409IZAY and AD9689BCPZ-1300, the ADS5402IZAY offers optimal balance of 800 Msps performance, LVDS simplicity, and proven multi-ADC synchronization-making it preferred for radar, EW, and broadband instrumentation where timing determinism and interface robustness outweigh raw speed or bit depth.
Availability
ADS5402IZAY is available at Aetrix Electronics and suitable for radar systems, ultra-wideband SDRs, and microwave receivers requiring stable component supply, long-term industrial temperature support (–40°C to +85°C), and guaranteed multi-year availability for embedded instrumentation programs.
Supply support for ADS5402IZAY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.
The ADS5402IZAY belongs to TI's high-speed ADC portfolio designed specifically for wideband receiver front ends in defense, test equipment, and infrastructure-emphasizing linearity, low jitter, and multi-device synchronization over generic sampling performance.
FAQ
What is the maximum sampling rate supported by the ADS5402IZAY?
The ADS5402IZAY supports a maximum sampling rate of 800 Msps, validated across its full industrial temperature range (–40°C to +85°C) with AVDD33 = 3.3 V and AVDD18/DVDD = 1.8 V. At this rate, it achieves 61.3 dBFS SNR and 74 dBc SFDR at 230 MHz input frequency, as specified in the SLAS936B datasheet. Operation above 800 Msps is not characterized or guaranteed for the ADS5402IZAY.
Does the ADS5402IZAY support synchronous operation with multiple ADCs?
Yes, the ADS5402IZAY supports deterministic multi-ADC synchronization via dedicated SYNCP/N and SYNCOUTP/N pins. When multiple ADS5402IZAY devices receive the same SYSNCIN signal, their internal clocks and digital logic reset simultaneously, enabling phase-aligned sampling. This capability is explicitly documented in the "Synchronization" section of the SLAS936B datasheet and verified in TI's reference designs for radar beamforming.
What power-saving modes does the ADS5402IZAY offer, and how fast is wake-up from each?
The ADS5402IZAY provides four power modes controlled via the ENABLE pin and SPI register x37: complete shutdown (2.5 ms wake-up, 7 mW), standby (100 µs wake-up, 7 mW), deep sleep (20 µs wake-up, 510 mW with auto-correction enabled), and light sleep (2 µs wake-up, 820 mW). All modes retain register settings, and wake-up timing is measured from ENABLE rising edge to first valid sample, as confirmed in the "Power Down Modes" section of SLAS936B.
Can the ADS5402IZAY be used with single-ended clock or analog input sources?
No-the ADS5402IZAY requires differential signaling for both clock (CLKINP/N) and analog inputs (INA_P/N, INB_P/N). Its internal architecture relies on differential pairs for common-mode noise rejection and optimal linearity. While external baluns can convert single-ended sources, TI's datasheet specifies performance only with true differential drive, and using single-ended signals degrades SNR and SFDR beyond published specifications for the ADS5402IZAY.
What is the purpose of the VCM and VREF pins on the ADS5402IZAY?
VCM (pin B14) outputs a stable 1.9 V common-mode voltage used to bias external analog circuitry (e.g., baluns, filters) to match the ADC's internal input stage; VREF (pin A14) provides a 2.0 V reference for external components requiring precise voltage references. Both pins require 0.1 µF decoupling to AGND per the SLAS936B layout guidelines, and neither is an input-misconnecting them as inputs may damage the ADS5402IZAY.
ADS5402IZAY Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 196-LFBGA
- Packaging:
- Bulk
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 800M
- Number of Inputs:
- 2
- Input Type:
- Differential
- Data Interface:
- Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 2
- Architecture:
- Pipelined
- Reference Type:
- External, Internal
- Voltage - Supply, Analog:
- 1.7V ~ 1.9V, 3.15V ~ 3.45V
- Voltage - Supply, Digital:
- 1.7V ~ 1.9V
- Features:
- Simultaneous Sampling
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 196-NFBGA (12x12)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS5402IZAY FAQ
1.How can I place an order for ADS5402IZAY through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS5402IZAY on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS5402IZAY reliable?
The price and inventory of ADS5402IZAY are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS5402IZAY is usually 5 days.
3.What payment methods are accepted for ADS5402IZAY?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS5402IZAY transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS5402IZAY?
ADS5402IZAY orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS5402IZAY order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS5402IZAY?
For technical support, including ADS5402IZAY datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS5402IZAY requirements.
6.How does Aetrix verify that ADS5402IZAY is sourced from the original manufacturer or authorized distributors?
All ADS5402IZAY products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS5402IZAY meets industry standards.
7.What is the process for return or replacement of ADS5402IZAY?
All ADS5402IZAY units undergo pre-shipment inspection (PSI). If there is an issue with ADS5402IZAY, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS5402IZAY part is unused and in its original packaging.
Return procedure for ADS5402IZAY:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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