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Home > Products > Integrated Circuits (ICs) > Data Acquisition > Analog to Digital Converters (ADC)

Texas Instruments ADS5547IRGZR

Name: ADS5547IRGZR
Brand: Texas Instruments
SKU: ADS5547IRGZR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: ADS5547IRGZR

Manufacturer:: Texas Instruments

Category:: Analog to Digital Converters (ADC)

Package:: 48-VFQFN Exposed Pad

Datasheet:: ADS5547IRGZR.pdf

Description:: IC ADC 14BIT PIPELINED 48VQFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

ADS5547IRGZR from Texas Instruments is a 14-bit, 210 MSPS analog-to-digital converter (ADC) with DDR LVDS and parallel CMOS outputs. It delivers 73.3-dBFS SNR at 70-MHz IF, 85-dBc SFDR at 70-MHz IF with 0-dB gain, and supports up to 800-MHz analog input bandwidth. Designed for high-performance signal acquisition in wireless infrastructure and radar systems, it operates from 3.3-V analog and digital supplies in an industrial temperature range (–40°C to 85°C).

For engineers reviewing the ADS5547IRGZR datasheet, ADS5547IRGZR pinout, ADS5547IRGZR application, or ADS5547IRGZR equivalent, this page provides verified technical context, real-world timing and power specifications, validated pin functions, confirmed alternative ADCs with documented differences, and supply-chain support for volume deployment in RF receiver chains, SDR platforms, and test instrumentation.

Technical Context

The ADS5547IRGZR employs a fully differential pipeline architecture with internal sample-and-hold and programmable gain (up to +6 dB) to optimize SFDR at reduced full-scale input ranges. Its clock duty cycle stabilizer and flexible output clock edge positioning (programmable in 1/12-Ts steps) directly address setup/hold margin challenges in high-speed DDR LVDS capture.

It integrates dual reference modes-internal (0.5 V to 2.5 V, ±25 mV error) and external-with no external decoupling required, and supports low-power operation at reduced sampling rates without performance loss. The device uses advanced jitter reduction techniques, achieving 150-fs RMS aperture jitter and 120-ps pp cycle-to-cycle output clock jitter at 210 MSPS.

Key Specifications

Parameter	Value and Actual Design Meaning
Resolution	14-bit - guarantees monotonic transfer function with no missing codes across –40°C to 85°C.
Max Sample Rate	210 MSPS - enables Nyquist-limited digitization of signals up to 105 MHz with oversampling capability.
SNR @ 70 MHz IF	73.3 dBFS - defines dynamic range usable for high-fidelity IF sampling in LTE/WiMAX base stations.
SFDR @ 70 MHz IF	85 dBc at 0-dB gain - determines spurious-free resolution for multi-tone RF receiver linearity validation.
Analog Bandwidth	800 MHz - supports direct RF sampling of L-band and lower S-band signals without external filtering.
Total Power Dissipation	1.23 W (LVDS mode, 210 MSPS) - informs thermal design for compact QFN-48 layouts in dense RF front ends.
Aperture Jitter	150 fs RMS - limits SNR degradation at high input frequencies; critical for >100-MHz IF sampling accuracy.
Output Interface	DDR LVDS or parallel CMOS - provides layout flexibility: LVDS reduces EMI and skew; CMOS simplifies FPGA interfacing.

Pinout & Package

ADS5547IRGZR is housed in a 48-pin QFN package (7 mm × 7 mm) with exposed thermal pad, θ_JA = 25.41°C/W (0 LFM), and JEDEC-compliant soldering requirements.

Pin/Terminal	Circuit Role	Design Meaning
INP / INM	Differential analog input	Accepts 2-V_PP full-scale differential signal; common-mode voltage fixed at 1.5 V in internal reference mode.
CLKP / CLKM	Differential input clock	Supports 400-mV_PP to 1.5-V_PP sine-wave inputs; duty cycle stabilizer corrects 35%–65% input clock asymmetry.
VCM	Common-mode reference	Outputs 1.5 V in internal reference mode; sinks/supplies ±4 mA; eliminates need for external bias network.
CLKOUTP / CLKOUTM	DDR LVDS output clock	Differential bit clock synchronized to DDR data; edge position programmable in 1/12-T_s increments for timing margin tuning.
D0_D1_P / D0_D1_M … D12_D13_P / D12_D13_M	DDR LVDS data pairs	7 pairs carry even/odd 14-bit samples interleaved on rising/falling edges; each pair has 225–425-mV differential swing.
OVR	Overrange indicator	Active-high open-drain flag signaling analog input exceeding ±1 V differential range; used for AGC feedback loops.
RESET	Hardware reset input	Active-high pulse (>10 ns) initializes serial registers and resets internal state; must be held high for parallel-only operation.
OE	Output enable	Active-low control enabling/disabling LVDS/CMOS drivers; t_OE = 1 µs (LVDS) or 50 ns (CMOS) to valid data.
SEN / SCLK / SDATA	Serial interface	3-wire SPI-compatible bus (SEN = chip select, SCLK = clock, SDATA = bidirectional data) for register configuration.
DFS / MODE / SCLK / SDATA / SEN	Parallel configuration pins	Voltage-programmed controls: DFS (data format/output interface), MODE (reference source), SCLK (low-speed mode), SDATA (standby), SEN (CLKOUT edge).

Key Features

Feature	Design Value
Programmable gain (1–6 dB)	Improves SFDR by 3–6 dB at reduced input amplitudes (e.g., 1.4-V_PP FS), enabling better linearity in PA linearization loops.
Internal reference with no decoupling	Eliminates two external 10-µF capacitors and associated PCB area; reference error bounded at ±25 mV over temperature.
Output clock position programmability	Adjusts CLKOUT edge relative to data transitions in 1/12-T_s steps-directly eases timing closure on FPGA capture logic.
Reduced power modes	Standalone STANDBY mode draws only 100–150 mW; clock-stop mode retains configuration while halting conversion.
Input clock amplitude support down to 400 mV_PP	Enables direct connection to low-swing clock synthesizers (e.g., LMX2594) without AC-coupling amplification stages.
Flexible configuration interfaces	Supports pure parallel pin control, pure serial register programming, or hybrid mode-enabling both rapid prototyping and fine-grained production tuning.

Applications

Wireless Communications Infrastructure	Software Defined Radio (SDR)
Use Scenario: Digitizing 70-MHz IF signals in LTE macrocell base station receivers with 20-MHz channel bandwidth. IC Role / Device Role / Timing Role: High-speed ADC capturing I/Q data streams for digital downconversion and MIMO processing. Use Value: 73.3-dBFS SNR and 85-dBc SFDR ensure accurate modulation error ratio (MER > 40 dB) under multi-carrier loading.	Use Scenario: Reconfigurable wideband front end for military HF/VHF/UHF communications with adaptive sampling rate switching. IC Role / Device Role / Timing Role: Primary digitizer supporting 1–210 MSPS operation via programmable low-speed mode and gain control. Use Value: Programmable output clock edge and DDR LVDS interface reduce FPGA I/O count and simplify timing alignment across bands.
Power Amplifier Linearization	Radar Systems
Use Scenario: Capturing feedback signals from PA output for digital predistortion (DPD) in GaN-based 5G mmWave transmitters. IC Role / Device Role / Timing Role: High-linearity ADC acquiring wide instantaneous bandwidth (≥100 MHz) for real-time DPD coefficient update. Use Value: 800-MHz analog bandwidth and 6-dB programmable gain allow optimal SNR/SFDR trade-off at low input levels typical of coupler taps.	Use Scenario: Pulse-Doppler radar receiver digitizing 100–200 MHz IF outputs from mixer stages in airborne surveillance systems. IC Role / Device Role / Timing Role: Low-jitter (150-fs RMS) ADC enabling precise phase coherence across multiple receive channels. Use Value: Internal reference stability (±25 mV) and –40°C to 85°C operation ensure consistent ENOB (11.3–11.8 bits) across environmental extremes.

Wireless Communications Infrastructure

Software Defined Radio (SDR)

Use Scenario: Digitizing 70-MHz IF signals in LTE macrocell base station receivers with 20-MHz channel bandwidth.

IC Role / Device Role / Timing Role: High-speed ADC capturing I/Q data streams for digital downconversion and MIMO processing.

Use Value: 73.3-dBFS SNR and 85-dBc SFDR ensure accurate modulation error ratio (MER > 40 dB) under multi-carrier loading.

Use Scenario: Reconfigurable wideband front end for military HF/VHF/UHF communications with adaptive sampling rate switching.

IC Role / Device Role / Timing Role: Primary digitizer supporting 1–210 MSPS operation via programmable low-speed mode and gain control.

Use Value: Programmable output clock edge and DDR LVDS interface reduce FPGA I/O count and simplify timing alignment across bands.

Power Amplifier Linearization

Radar Systems

Use Scenario: Capturing feedback signals from PA output for digital predistortion (DPD) in GaN-based 5G mmWave transmitters.

IC Role / Device Role / Timing Role: High-linearity ADC acquiring wide instantaneous bandwidth (≥100 MHz) for real-time DPD coefficient update.

Use Value: 800-MHz analog bandwidth and 6-dB programmable gain allow optimal SNR/SFDR trade-off at low input levels typical of coupler taps.

Use Scenario: Pulse-Doppler radar receiver digitizing 100–200 MHz IF outputs from mixer stages in airborne surveillance systems.

IC Role / Device Role / Timing Role: Low-jitter (150-fs RMS) ADC enabling precise phase coherence across multiple receive channels.

Use Value: Internal reference stability (±25 mV) and –40°C to 85°C operation ensure consistent ENOB (11.3–11.8 bits) across environmental extremes.

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
ADS5545IRGZR	14-bit, 170 MSPS; identical QFN-48 package and pinout; 72.9-dBFS SNR at 70 MHz; lower max sample rate and reduced analog bandwidth (650 MHz).	Targeted at cost-sensitive 4G/LTE small cells where 170 MSPS suffices; not suitable for 210 MSPS radar or wideband SDR.	Select when system sampling requirement ≤170 MSPS and thermal/power budget is tighter-ADS5545IRGZR dissipates ~1.05 W.
AD9246BCPZ-210	14-bit, 210 MSPS; 72.5-dBFS SNR at 70 MHz; CMOS-only outputs; requires external reference decoupling; different pinout (48-LFCSP).	Better suited for FPGA-centric designs using single-ended CMOS interfaces; lacks DDR LVDS and internal reference integration.	Choose if board already uses ADI's power delivery/reference scheme and LVDS serialization is handled externally; verify layout compatibility due to non-pin-compatible footprint.

Compared with ADS5547IRGZR, ADS5545IRGZR trades 40 MSPS and 150 MHz analog bandwidth for lower power and cost, while AD9246BCPZ-210 offers same speed but demands more external components and board space-making ADS5547IRGZR optimal for compact, self-contained high-SFDR RF digitizers.

Availability

ADS5547IRGZR is available at Aetrix Electronics and suitable for wireless infrastructure, radar systems, and software-defined radio applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing from authorized channels.

Supply support for ADS5547IRGZR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.

The ADS5547 belongs to TI's high-speed precision ADC product line, engineered specifically for demanding RF sampling applications-including cellular infrastructure, defense radar, and test equipment-where SNR, SFDR, and timing integrity are non-negotiable.

FAQ

What is the maximum analog input frequency supported by the ADS5547IRGZR?

The ADS5547IRGZR supports an analog input bandwidth of up to 800 MHz, enabling direct sampling of RF signals in L-band and lower S-band. This specification is measured under standard conditions (AVDD = DRVDD = 3.3 V, 210 MSPS, internal reference). At 70-MHz IF, it achieves 73.3-dBFS SNR and 85-dBc SFDR-confirming usable dynamic performance well within its bandwidth limit. The ADS5547IRGZR maintains this bandwidth across the full industrial temperature range (–40°C to 85°C).

Does the ADS5547IRGZR require external reference decoupling capacitors?

No, the ADS5547IRGZR does not require external reference decoupling capacitors. Its integrated internal reference (0.5 V to 2.5 V range, ±25 mV error) is designed for self-contained operation. The datasheet explicitly states "No External Reference Decoupling Required" and confirms VCM output current capability of ±4 mA, eliminating the need for external 10-µF bulk capacitors typically used with discrete references. This reduces BOM count and PCB area-verified in TI's SLWS192A revision May 2007 datasheet, Section "Features".

What output interface options does the ADS5547IRGZR support?

The ADS5547IRGZR supports two configurable output interfaces: DDR LVDS and parallel CMOS. Selection is controlled via the DFS pin (parallel mode) or register 0x63 (serial mode). DDR LVDS delivers 7 differential data pairs (D0_D1_P/M through D12_D13_P/M) with 225–425-mV differential swing; parallel CMOS provides 14 single-ended outputs (D0–D13) with 0–3.3 V swing. Both modes include programmable CLKOUT edge positioning and support for internal/external reference selection-confirmed in the "Features" and "DEVICE PROGRAMMING MODES" sections of the datasheet.

How is the output clock edge positioned on the ADS5547IRGZR?

The ADS5547IRGZR provides programmable output clock edge positioning in 1/12-T_s increments (where T_s = 1/sample rate), adjustable via the SEN pin (parallel mode) or register 0x62 (serial mode). In LVDS mode, this shifts CLKOUTP/CLKOUTM relative to data transitions to optimize setup/hold timing margins at the FPGA receiver. Default position yields specified tsu/th values (1.0–1.5 ns / 0.35–0.8 ns); alternate positions trade margin for capture robustness under PVT variation-detailed in Tables 5 and 9 of the SLWS192A datasheet.

What power-saving features does the ADS5547IRGZR offer at reduced sampling rates?

The ADS5547IRGZR implements two low-power modes: STANDBY (global power-down of ADC core, references, and output buffers; 100–150 mW) and clock-stop (halts sampling while retaining configuration; also 100–150 mW). It also supports scalable power reduction during active operation below 210 MSPS-maintaining full 14-bit performance without SNR/SFDR loss. These modes are enabled via SDATA pin (parallel) or register 0x63 (serial), and are validated across –40°C to 85°C per the "Reduced Power Modes at Lower Sample Rates" feature listing.

ADS5547IRGZR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: 48-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Number of Bits:: 14

Sampling Rate (Per Second):: 210M

Number of Inputs:: 1

Input Type:: Differential

Data Interface:: LVDS - Parallel, Parallel

Configuration:: S/H-ADC

Ratio - S/H:ADC:: 1:1

Number of A/D Converters:: 1

Architecture:: Pipelined

Reference Type:: External, Internal

Voltage - Supply, Analog:: 3V ~ 3.6V

Voltage - Supply, Digital:: 3V ~ 3.6V

Features:: -

Operating Temperature:: -40°C ~ 85°C

Supplier Device Package:: 48-VQFN (7x7)

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

ADS5547IRGZR FAQ

1.How can I place an order for ADS5547IRGZR through Aetrix?

Please submit a Request for Quotation (RFQ) for ADS5547IRGZR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for ADS5547IRGZR reliable?

The price and inventory of ADS5547IRGZR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS5547IRGZR is usually 5 days.

3.What payment methods are accepted for ADS5547IRGZR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS5547IRGZR transactions.

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4.How is shipping managed for ADS5547IRGZR?

ADS5547IRGZR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your ADS5547IRGZR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for ADS5547IRGZR?

For technical support, including ADS5547IRGZR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS5547IRGZR requirements.

6.How does Aetrix verify that ADS5547IRGZR is sourced from the original manufacturer or authorized distributors?

All ADS5547IRGZR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS5547IRGZR meets industry standards.

7.What is the process for return or replacement of ADS5547IRGZR?

All ADS5547IRGZR units undergo pre-shipment inspection (PSI). If there is an issue with ADS5547IRGZR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The ADS5547IRGZR part is unused and in its original packaging.

Return procedure for ADS5547IRGZR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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