Texas Instruments ADS58J89EVM

Overview

ADS58J89EVM from Texas Instruments is an evaluation module designed to characterize the ADS58J89 14-bit, 4-channel, 500-MSPS JESD204B analog-to-digital converter and its companion LMK04828 ultra-low-jitter clock jitter cleaner. It supports transformer-coupled analog inputs, FMC-based interfacing with FPGA development platforms (Xilinx KC705, Altera Arria V), and full software control via High Speed Data Converter Pro GUI.

For engineers reviewing the ADS58J89EVM datasheet, ADS58J89EVM pinout, ADS58J89EVM application, or ADS58J89EVM equivalent, this page delivers verified hardware interface details, JESD204B subclass 1 timing configuration support, FMC connector compatibility, burst-mode trigger operation, and integrated clocking architecture for high-speed data acquisition system validation.

Technical Context

The ADS58J89EVM implements a complete JESD204B subclass 1 signal chain: the ADS58J89 ADC operates at up to 500 MSPS with 14-bit resolution, configurable decimation filters, SNRBoost, and burst-mode triggering; the LMK04828 provides dual-PLL clock generation with 2.5/3.0 GHz VCOs, 14 programmable outputs, and precise SYSREF synchronization aligned to LMFC periods.

Hardware interfaces include an FMC connector (male) for JESD204B data and clock routing, four SMA analog input ports (J1/J2/J22/J23), TRIG_IN/TRIG_OUT for external burst control, USB for SPI configuration, and jumper-selectable reference sources (10-MHz oscillator or external REF OSC_IN).

Key Specifications

Availability

ADS58J89EVM is available at Aetrix Electronics and suitable for high-speed data converter evaluation, JESD204B interface validation, and RF receiver front-end prototyping requiring stable component supply and full design documentation access.

Supply support for ADS58J89EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data conversion technologies.

The ADS58J89EVM belongs to TI's high-speed data converter evaluation platform family, engineered to accelerate development of wideband communications, radar, test equipment, and software-defined radio systems with JESD204B-compliant signal chains.

FAQ

What is the primary function of the ADS58J89EVM?

The ADS58J89EVM is a Texas Instruments evaluation module built around the ADS58J89 14-bit, 4-channel, 500-MSPS ADC and the LMK04828 clock jitter cleaner. Its primary function is to enable rapid performance characterization, JESD204B link validation, and system-level integration testing of high-speed analog-to-digital conversion in RF and communications applications. The ADS58J89EVM provides full hardware and software infrastructure-including FMC interface, GUI-controlled SPI registers, and transformer-coupled analog inputs-to evaluate the ADS58J89EVM in real-world signal chain configurations.

Which FPGA development boards are compatible with the ADS58J89EVM?

The ADS58J89EVM is explicitly verified for interoperability with the Xilinx KC705 and Altera Arria V FPGA evaluation platforms via its standard FMC connector. It also integrates directly with TI's TSW14J56EVM JESD204B capture card. All three platforms support JESD204B subclass 1 timing, enabling synchronized data capture and clock distribution using the ADS58J89EVM's LMK04828-generated DCLK and SYSREF signals. Compatibility relies on correct L/M/F/K parameter alignment between the ADS58J89EVM and host FPGA firmware.

How does the burst-mode triggering work on the ADS58J89EVM?

Burst-mode triggering on the ADS58J89EVM allows the ADS58J89 to output full 14-bit resolution data for a programmable duration upon receiving a trigger event-followed by lower-resolution output during idle periods. Triggers can originate from three sources: pushbutton SW2, external SMA input J5 (TRIG_IN), or software command via the High Speed Data Converter Pro GUI. The triggered signal is latched and delayed before appearing on J26 (TRIG_OUT), ensuring precise alignment with high-resolution sample capture on downstream devices like the TSW14J56EVM. This functionality is implemented entirely within the ADS58J89EVM's hardware and firmware stack.

What clocking options does the ADS58J89EVM support?

The ADS58J89EVM supports multiple clocking configurations: default operation uses the onboard 10-MHz oscillator feeding the LMK04828's PLL1, which locks a 2.5/3.0-GHz VCO in PLL2 to generate device clocks (e.g., 500 MHz for ADS58J89) and SYSREF signals. An external reference can be applied via J14 (REF OSC_IN), and an external ADC clock may be injected at J19 (EXT_ADC_CLK). Clock outputs-including DCLK and SYSREF pairs-are configurable in format (LVPECL/LVDS), frequency (via integer dividers), phase, and delay using the GUI's LMK04828 Clock Outputs and SYSREF tabs.

Where can I obtain the schematics and layout files for the ADS58J89EVM?

Schematics, bill-of-materials (BOM), and PCB layout files for the ADS58J89EVM are publicly available in the design package under the ADS58J89EVM product folder on www.ti.com. These resources are provided by Texas Instruments to support design reuse, signal integrity analysis, and custom adaptation of the evaluation platform. No registration or NDA is required to access these files, and they correspond precisely to the production version of the ADS58J89EVM board shipped by TI.