Texas Instruments ADS6122EVM

Overview

ADS6122EVM from Texas Instruments is an evaluation module designed to characterize the ADS6122 12-bit, 65-MSPS analog-to-digital converter under controlled analog input, clock, and supply conditions. It supports CMOS parallel output (12-bit offset binary), transformer-coupled or THS4509-amplified differential input paths, and configurable clock routing via transformer or CDCP1803 LVDS fanout. The EVM enables SNR/SFDR measurement of high-speed ADCs in test benches for communications and instrumentation.

For engineers reviewing the ADS6122EVM datasheet, ADS6122EVM pinout, ADS6122EVM application, or ADS6122EVM equivalent, this page details its hardware configuration options, SPI register control interface, FPGA integration paths (TSW1100/TSW1200), breakout board connectivity, and jumper-based mode selection for ADC evaluation workflows.

Technical Context

The ADS6122EVM implements a four-layer FR-4 PCB with split ground plane and dedicated analog/digital power domains (J11/J13). It supports dual analog input signal paths: single-ended SMA input J8 converted to ac-coupled differential via transformer, or single-ended SMA input J10 amplified and converted by THS4509 with selectable dc/ac coupling and common-mode biasing.

Clock distribution includes transformer-coupled single-ended-to-differential conversion (T3) and optional CDCP1803 1:3 LVDS fanout for multi-ADC synchronization. Digital outputs route to Samtec QSO-060-01-F-D-A connector (J10), supporting logic analyzer capture, TSW1100/TSW1200 FPGA platforms, or custom digital interface boards.

Key Specifications

Availability

ADS6122EVM is available at Aetrix Electronics and suitable for high-speed ADC characterization, RF receiver chain validation, and mixed-signal test bench development requiring stable component supply and documented evaluation infrastructure.

Supply support for ADS6122EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications systems.

The ADS61xx EVM product line was developed to accelerate evaluation of TI's low-power, high-resolution pipeline ADCs-including the ADS6122-by providing validated signal chain topologies, calibrated jumper configurations, and FPGA-ready interconnects.

FAQ

What is the primary function of the ADS6122EVM?

The ADS6122EVM is an evaluation module built specifically to assess the performance of the ADS6122 12-bit, 65-MSPS analog-to-digital converter. It provides configurable analog input paths (transformer or THS4509 amplifier), multiple clock routing options, parallel CMOS digital output access, and SPI-based register control. The ADS6122EVM enables engineers to measure key metrics such as SNR, SFDR, and ENOB under real-world signal, reference, and supply conditions without custom PCB design.

Which ADC models does the ADS6122EVM support besides the ADS6122?

The ADS6122EVM is part of the unified ADS61xx/ADS61B23 EVM platform and supports evaluation of ADS6122, ADS6123, ADS6124, ADS6125, ADS6142, ADS6143, ADS6144, ADS6145, and ADS61B23 devices. All share identical board-level architecture, jumper configurations, and signal chain topology, though individual ADC-specific features (e.g., LVDS output, resolution, sample rate) require corresponding jumper and software settings per device datasheet.

How does the ADS6122EVM handle analog input signal conditioning?

The ADS6122EVM offers two distinct analog input paths: a transformer-coupled path (SMA J8) for passive ac-coupled differential conversion, and an active THS4509 amplifier path (SMA J10) providing 10 dB gain and configurable dc/ac coupling. Jumpers JP5 and JP6 select between paths; dc coupling requires R21 population and VCC/–VCC biasing (4 V / –1 V), while ac coupling uses R37/R45 voltage dividers and C75/C77 capacitors. This flexibility ensures optimal noise and distortion performance across frequency bands.

Can the ADS6122EVM be used with FPGA development platforms?

Yes, the ADS6122EVM natively interfaces with TI's TSW1200 FPGA platform and supports TSW1100 via a companion CMOS breakout board. For TSW1100, users connect the breakout board to J2 (Channel 2) and update Supported_ADCs.txt; for TSW1200, direct plug-in is enabled with optional FPGA reprogramming for SPI control. Surface-mount jumpers (JP2–JP4, JP7, JP8) and through-hole jumpers (J2–J7) must be reconfigured to route SEN, SCLK, SDATA, and clock signals from the FPGA to the ADS6122EVM.

What software tools are provided for configuring the ADS6122 on the ADS6122EVM?

The ADS6122EVM ships with TI's ADC SPI Control Software, which runs on Windows and communicates via USB to configure ADS6122 registers not accessible in default parallel mode. It supports manual register writes, script-based batch programming, and one-click presets for common functions (reset, output format, reference selection, course gain). The software installs USB drivers and provides a GUI with real-time command logging, enabling precise control of ADS6122 features including power-down, test modes, and LVDS/CMOS output configuration.