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Texas Instruments ADS6122IRHBT
- Part No.:
- ADS6122IRHBT
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
ADS6122IRHBT.pdf
- Description:
- IC ADC 12BIT PIPELINED 32VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:739
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Product details
Overview
ADS6122IRHBT from Texas Instruments is a 12-bit, 65 MSPS analog-to-digital converter with DDR LVDS or parallel CMOS outputs, internal reference, and programmable coarse/fine gain. It delivers 71.6 dBFS SINAD at 10 MHz input (0 dB gain), 84 dBc SFDR at 170 MHz (3.5 dB gain), and operates from 3.3 V analog / 1.8–3.3 V digital supplies in industrial temperature range (–40°C to 85°C). It serves high-performance data acquisition in radar front-ends.
For engineers reviewing the ADS6122IRHBT datasheet, ADS6122IRHBT pinout, ADS6122IRHBT application, or ADS6122IRHBT equivalent, key selection criteria include its 65 MSPS sampling rate, LVDS/CMOS interface flexibility, 3.5 dB coarse + 6 dB fine gain control, clock duty cycle stabilizer, and QFN-32 package compatibility within the ADS612X family.
Technical Context
The ADS6122IRHBT uses a high-bandwidth sample-and-hold with low-jitter clock buffer to maintain 69.8 dBFS SINAD at 170 MHz input under 3.5 dB coarse gain. Its dual-output architecture supports either DDR LVDS (3.3 V DRVDD, 3.5 mA current, 100 Ω load) or parallel CMOS (1.8–3.3 V DRVDD), with programmable output clock position and drive strength for timing margin optimization.
Configuration occurs via 3-wire serial interface (SEN/SCLK/SDATA) or dedicated parallel pins (SCLK/SEN/SDATA/PDN), enabling power-up state definition without firmware. Internal reference eliminates external decoupling; external reference mode supports 1.45–1.55 V VCM with ±20 mV ΔVREF error.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Sampling Rate | 65 MSPS maximum - defines real-time bandwidth limit for baseband signal digitization in SDR and test equipment. |
| Resolution | 12 bits with no missing codes - guarantees monotonic transfer function and deterministic code transitions across full scale. |
| SINAD | 71.6 dBFS at 10 MHz, 0 dB gain - determines effective dynamic range for high-fidelity IF sampling in wireless infrastructure. |
| SFDR | 84 dBc at 170 MHz, 3.5 dB coarse gain - sets spurious-free input amplitude ceiling before harmonic distortion dominates. |
| Power Consumption | 285 mW total (CMOS mode) - enables thermal management in dense RF module layouts with minimal heatsinking. |
| Package | 32-pin QFN (5 mm × 5 mm) - provides compact footprint and low-inductance ground path for high-frequency analog integrity. |
| Supply Voltages | AVDD = 3.3 V (3.0–3.6 V), DRVDD = 1.8–3.3 V - supports mixed-signal voltage domain partitioning and legacy 3.3 V or modern 1.8 V logic interfacing. |
Pinout & Package
ADS6122IRHBT is housed in a 32-pin QFN package (RHB designation) with exposed thermal pad. Pin functions are validated per TI SLAS560A datasheet Figure 1 and Table 1–3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INP / INM | Differential analog input | Accepts 2 VPP differential signal; 450 MHz analog bandwidth supports Nyquist zone 1–2 sampling. |
| CLKP / CLKM | Differential clock input | Supports sine/LVPECL/LVDS/LVCMOS clocks down to 400 mVPP; internal duty cycle stabilizer corrects skew. |
| VCM | Common-mode voltage reference | Sets input common-mode level to 1.5 V; externally driven in external reference mode (1.45–1.55 V). |
| CLKOUTP / CLKOUTM | DDR LVDS output clock | Provides synchronized 65 MHz DDR clock for data capture; programmable phase position eases setup/hold timing. |
| D0_D1_P through D10_D11_M | DDR LVDS data pairs | 12-bit parallel data transmitted on both clock edges; internal termination eliminates external resistors. |
| SCLK / SEN / SDATA / RESET / PDN | Configuration and control | Enable serial programming (3-wire) or parallel boot-state setup; PDN controls global power-down (30 mW standby). |
| AVDD / AGND / DRVDD / DRGND | Power domains | Separate analog/digital supplies reduce noise coupling; AGND–DRGND voltage limited to ±0.3 V prevents ground bounce errors. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable coarse/fine gain | 3.5 dB coarse + up to 6 dB fine gain improves SFDR at reduced full-scale inputs without external amplifiers. |
| DDR LVDS or CMOS output interface | Reduces PCB trace count by 50% vs. single-data-rate LVDS and supports legacy CMOS FPGA interfaces. |
| Internal reference with no external decoupling | Eliminates two 10 µF capacitors and associated board area, simplifying layout and reducing BOM cost. |
| Output clock position programmability | Adjusts CLKOUT phase relative to data edges to compensate for PCB trace skew and FPGA input delays. |
| 3-wire serial + parallel pin configuration | Enables flexible startup: hardware-defined state for rapid deployment or register-level tuning for precision calibration. |
Applications
| Radar Systems | Test and Measurement Instrumentation |
|---|---|
Use Scenario: Digitizing intermediate frequency (IF) signals from pulsed Doppler radar receivers operating at 170 MHz. IC Role / Device Role / Timing Role: ADC front-end capturing 65 MSPS sampled IF data with 84 dBc SFDR to resolve weak targets amid strong clutter. Use Value: 3.5 dB coarse gain extends dynamic range for low-amplitude echo detection while maintaining spurious-free performance. | Use Scenario: High-speed waveform digitization in portable spectrum analyzers requiring >60 dB SFDR up to 230 MHz. IC Role / Device Role / Timing Role: Core sampling engine delivering 71.7 dBFS SINAD at 10 MHz and 69.1 dBFS at 230 MHz in LVDS mode. Use Value: DDR LVDS interface reduces FPGA I/O pin count and timing closure complexity versus parallel CMOS. |
| Software Defined Radio | Medical Imaging |
Use Scenario: Baseband sampling in multi-carrier LTE femtocell transceivers with adaptive gain control. IC Role / Device Role / Timing Role: 12-bit ADC supporting reconfigurable bandwidth via programmable gain and clock rate scaling. Use Value: Parallel pin control (SCLK/SEN) allows gain/output format selection at power-up without host processor intervention. | Use Scenario: Ultrasound beamformer digitizing 10–20 MHz echo signals with low harmonic distortion. IC Role / Device Role / Timing Role: High-SFDR ADC minimizing third-harmonic artifacts (HD3 = 84 dBc at 170 MHz) in time-domain imaging. Use Value: Internal reference stability (±5 mV ΔVREF) ensures consistent gain calibration across temperature in portable scanners. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS6123IRHBT | 80 MSPS max sampling rate; 318 mW power; 71.5 dBFS SINAD at 10 MHz (0 dB gain) | Higher throughput for wider IF bandwidths; increased power and thermal load | Select when system requires >65 MSPS sampling without upgrading to 105 MSPS ADS6124. |
| ADS5272IPFP | 12-bit, 65 MSPS, 32-QFN, but with serial LVDS (not DDR) and no internal reference | Requires external reference and clock conditioning circuitry; lower channel count density | Choose if DDR LVDS is unnecessary and external reference design is already established. |
Compared with ADS6123IRHBT and ADS5272IPFP, the ADS6122IRHBT offers lowest power (285 mW) and integrated reference among pin-compatible ADS612X variants, while ADS5272IPFP trades internal resources for simplified LVDS serialization-making ADS6122IRHBT optimal for space-constrained, self-contained IF digitizers.
Availability
ADS6122IRHBT is available at Aetrix Electronics and suitable for radar systems, software defined radio, and medical ultrasound requiring stable component supply, long-term obsolescence planning, and guaranteed lot traceability.
Supply support for ADS6122IRHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance data converters for industrial, automotive, and communications markets.
The ADS612X product line delivers low-power, high-SFDR ADCs for IF sampling in wireless infrastructure and instrumentation, emphasizing integration (internal reference, clock stabilizer) and interface flexibility (LVDS/CMOS).
FAQ
What is the maximum sampling rate supported by the ADS6122IRHBT?
The ADS6122IRHBT supports a maximum sampling rate of 65 MSPS, as specified in the SLAS560A datasheet. This rate is fixed for the ADS6122 variant and distinguishes it from higher-speed members of the ADS612X family (e.g., ADS6123 at 80 MSPS). Operation above 65 MSPS is not functional or characterized.
Does the ADS6122IRHBT require external decoupling capacitors for its internal reference?
No, the ADS6122IRHBT does not require external decoupling capacitors for its internal reference. The device integrates reference circuitry that eliminates traditional reference pins and associated external decoupling, as confirmed in the Features section and Electrical Characteristics table of the SLAS560A datasheet.
Can the ADS6122IRHBT operate with a 1.8 V digital supply voltage?
Yes, the ADS6122IRHBT supports DRVDD from 1.8 V to 3.3 V for its digital output buffers. In CMOS mode, 1.8 V DRVDD reduces digital supply current (e.g., 4.0 mA typical at 65 MSPS), enabling compatibility with low-voltage FPGAs while maintaining valid logic levels (VOH = DRVDD, VOL = 0 V).
What clock input types are compatible with the ADS6122IRHBT?
The ADS6122IRHBT accepts sine wave, LVCMOS, LVPECL, and LVDS differential clock inputs. Minimum differential amplitude is 400 mVPP for sine, ±0.8 VPP for LVPECL, ±0.35 VPP for LVDS, and 3.3 VPP for LVCMOS-all ac-coupled, per the Recommended Operating Conditions table in SLAS560A.
How is the output interface (LVDS vs. CMOS) configured on the ADS6122IRHBT?
The output interface is configured using the SEN pin in parallel mode: SEN = 0 V selects DDR LVDS, (5/8) AVDD selects parallel CMOS with straight binary format, and AVDD selects parallel CMOS with 2s complement. Serial interface register 0x00 bit
ADS6122IRHBT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 65M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 3V ~ 3.6V
- Voltage - Supply, Digital:
- 1.65V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-VQFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS6122IRHBT FAQ
1.How can I place an order for ADS6122IRHBT through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS6122IRHBT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS6122IRHBT reliable?
The price and inventory of ADS6122IRHBT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS6122IRHBT is usually 5 days.
3.What payment methods are accepted for ADS6122IRHBT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS6122IRHBT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS6122IRHBT?
ADS6122IRHBT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS6122IRHBT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS6122IRHBT?
For technical support, including ADS6122IRHBT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS6122IRHBT requirements.
6.How does Aetrix verify that ADS6122IRHBT is sourced from the original manufacturer or authorized distributors?
All ADS6122IRHBT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS6122IRHBT meets industry standards.
7.What is the process for return or replacement of ADS6122IRHBT?
All ADS6122IRHBT units undergo pre-shipment inspection (PSI). If there is an issue with ADS6122IRHBT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS6122IRHBT part is unused and in its original packaging.
Return procedure for ADS6122IRHBT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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