My Inquiry
My Account
Texas Instruments ADS6123IRHBR
- Part No.:
- ADS6123IRHBR
- Manufacturer:
- Texas Instruments
- Category:
- Analog to Digital Converters (ADC)
- Package:
- 32-VFQFN Exposed Pad
- Datasheet:
-
ADS6123IRHBR.pdf
- Description:
- IC ADC 12BIT PIPELINED 32VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,408
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADS6123IRHBR from Texas Instruments is a 12-bit, 80 MSPS analog-to-digital converter with dual-output interface support (DDR LVDS or parallel CMOS), 3.5 dB coarse gain + up to 6 dB programmable fine gain, and integrated reference. It operates from 3.3 V analog and 1.8–3.3 V digital supplies in a 32-pin QFN package, targeting high-performance data acquisition in wireless infrastructure and radar systems.
For engineers reviewing the ADS6123IRHBR datasheet, ADS6123IRHBR pinout, ADS6123IRHBR application, or ADS6123IRHBR equivalent, key selection criteria include its 80 MSPS sampling rate, SINAD of 71.5 dBFS at 10 MHz input (0 dB gain), SFDR of 93 dBc at same condition, LVDS/CMOS interface flexibility, and industrial temperature range (–40°C to 85°C) operation.
Technical Context
The ADS6123IRHBR employs a high-bandwidth sample-and-hold circuit and low-jitter clock buffer to maintain 69.2 dBFS SINAD and 83 dBc SFDR at 170 MHz input with 3.5 dB coarse gain. Its internal reference eliminates external decoupling requirements, while clock duty cycle stabilization supports robust timing across sine, LVPECL, LVDS, and LVCMOS inputs down to 400 mVPP.
Digital output configuration uses either a 3-wire serial interface (SCLK/SEN/SDATA) or dedicated parallel pins for power-up state control. Output clock position, drive strength, and LVDS current are programmable; latency is fixed at 9 clock cycles in both CMOS and DDR LVDS modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Sampling Rate | 80 MSPS maximum - enables digitization of IF signals up to 450 MHz analog bandwidth with adequate Nyquist margin. |
| Resolution & Linearity | 12-bit with no missing codes, ±1 LSB DNL, ±2 LSB INL - ensures monotonicity and accurate amplitude representation in measurement systems. |
| SINAD / SNR | 71.5 dBFS at 10 MHz (0 dB gain), 69.2 dBFS at 170 MHz (3.5 dB gain) - defines usable dynamic range for baseband and wideband receiver applications. |
| SFDR | 93 dBc at 10 MHz (0 dB gain), 83 dBc at 170 MHz (3.5 dB gain) - critical for detecting weak signals adjacent to strong interferers in SDR and PA linearization. |
| Power Consumption | 318 mW total (CMOS mode, 3.3 V DRVDD) - balances performance and thermal management in dense RF front-end layouts. |
| Supply Voltages | AVDD = 3.0–3.6 V; DRVDD = 1.8–3.3 V (CMOS) or 3.0–3.6 V (LVDS) - supports mixed-signal partitioning and low-voltage digital interfacing. |
| Operating Temperature | –40°C to +85°C - qualified for deployment in outdoor wireless infrastructure and industrial embedded environments. |
Pinout & Package
The ADS6123IRHBR is housed in a 5 mm × 5 mm, 32-pin QFN package (RHB) with exposed thermal pad. Pin functions align with the ADS612X family architecture and support differential analog input, dual-clock interface, DDR LVDS/CMOS data outputs, and serial/parallel configuration control.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| INP / INM | Differential analog input | Accepts 2 VPP full-scale differential signal; 7 pF input capacitance and >1 MΩ input resistance simplify anti-alias filter design. |
| CLKP / CLKM | Differential clock input | Supports LVPECL/LVDS/LVCMOS/sine clocks down to 400 mVPP; internal duty cycle stabilizer relaxes clock source requirements. |
| VCM | Common-mode voltage reference | Sets 1.5 V common-mode level for analog input; externally driven in external reference mode (1.45–1.55 V). |
| CLKOUTP / CLKOUTM | DDR LVDS output clock | Provides synchronized 80 MHz DDR clock for data capture; programmable position reduces setup/hold timing margin pressure. |
| D0_D1_P through D10_D11_M | DDR LVDS data pairs | Delivers 12-bit samples on both edges of CLKOUT; internal 100 Ω termination option simplifies PCB routing. |
| D0–D11 | Parallel CMOS data outputs | Single-ended outputs compatible with 1.8–3.3 V logic; drive strength programmable for varying load capacitance (≤5 pF or >5 pF). |
| SCLK / SEN / SDATA | Serial interface control | 3-wire SPI-compatible interface for configuring gain, output format, clock position, and LVDS current without requiring external logic. |
| PDN | Power-down control | Four states: normal, ADC standby, output buffer disable, global power-down - enables granular power management in battery-aware or burst-mode systems. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable coarse/fine gain | 3.5 dB coarse gain + 0–6 dB fine gain improves SFDR at reduced input ranges without external amplifiers. |
| Integrated reference system | Internal 1 V–2 V reference eliminates external reference ICs and decoupling capacitors, reducing BOM count and board area. |
| Flexible output interface | Selectable DDR LVDS or parallel CMOS output avoids FPGA I/O bank constraints and supports legacy or high-speed interconnects. |
| Configurable via parallel pins | SEN/SCLK/SDATA/PDN pins serve as hardware-strapped controls for LVDS/CMOS, reference mode, and data format - enables deterministic power-up behavior. |
| Low-latency deterministic timing | Fixed 9-cycle latency and programmable output clock position simplify timing closure in real-time processing pipelines. |
Applications
| Wireless Infrastructure Baseband | Software Defined Radio (SDR) |
|---|---|
Use Scenario: Digitizing 20–40 MHz IF signals in macrocell BTS receivers with multi-carrier WCDMA/LTE waveforms. IC Role / Device Role / Timing Role: High-SFDR ADC capturing wide instantaneous bandwidth while maintaining EVM under composite signal conditions. Use Value: 93 dBc SFDR at 10 MHz enables detection of –93 dBc adjacent channel leakage without additional analog filtering. | Use Scenario: Reconfigurable front-end in military/comms SDR platforms requiring rapid mode switching between narrowband and wideband waveforms. IC Role / Device Role / Timing Role: Programmable-gain, dual-interface ADC supporting both low-power CMOS and high-speed LVDS depending on host processor capability. Use Value: Parallel pin configuration allows boot-time selection of output mode, eliminating need for runtime reconfiguration firmware. |
| Power Amplifier Linearization | Radar Signal Acquisition |
Use Scenario: Capturing PA output for digital predistortion (DPD) feedback loops in active antenna systems. IC Role / Device Role / Timing Role: Low-latency, high-linearity ADC synchronizing precisely with transmit path to enable real-time adaptive correction. Use Value: 9-cycle fixed latency and programmable CLKOUT position allow deterministic alignment of feedback samples to Tx symbols. | Use Scenario: Pulse-Doppler radar digitizing intermediate frequency returns with high dynamic range to resolve small targets against clutter. IC Role / Device Role / Timing Role: Wide analog bandwidth (450 MHz) and high SFDR ADC enabling high-resolution range/velocity profiling. Use Value: 83 dBc SFDR at 170 MHz preserves target signature integrity when digitizing high-frequency chirp returns. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-speed ADC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADS6124IRHBR | 105 MSPS max sampling rate; higher power (374 mW); 0.2 dB better SINAD at 10 MHz (71.3 dBFS vs. 71.5 dBFS) | Required where >80 MSPS sampling is needed for wider IF bandwidth or higher Nyquist zones | Select ADS6124IRHBR if system requires ≥100 MSPS sampling; ADS6123IRHBR remains optimal for 80 MSPS-constrained designs seeking lower power. |
| ADS6122IRHBR | 65 MSPS max sampling rate; lower power (285 mW); identical 12-bit resolution and pinout | Suitable for cost-sensitive or thermally constrained applications with ≤65 MSPS bandwidth needs | ADS6122IRHBR offers lowest power in family; choose ADS6123IRHBR when 80 MSPS is required and 33 mW extra power is acceptable for increased throughput. |
Compared with ADS6124IRHBR and ADS6122IRHBR, the ADS6123IRHBR delivers the optimal balance of sampling speed (80 MSPS), power (318 mW), and SFDR (93 dBc) for mid-tier wireless and radar signal chains where 105 MSPS is excessive but 65 MSPS is insufficient.
Availability
ADS6123IRHBR is available at Aetrix Electronics and suitable for wireless infrastructure, software-defined radio, and radar signal acquisition requiring stable component supply across extended production lifecycles.
Supply support for ADS6123IRHBR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.
The ADS612X family was designed specifically for high-performance, low-power data acquisition in wireless infrastructure and instrumentation, emphasizing flexible interface options, integrated references, and deterministic timing behavior.
FAQ
What is the maximum sampling rate supported by the ADS6123IRHBR?
The ADS6123IRHBR supports a maximum sampling rate of 80 MSPS. This is confirmed in the device family datasheet SLAS560A, where ADS6123 is explicitly rated for 80 MSPS operation across the full industrial temperature range (–40°C to +85°C), with electrical characteristics validated at this rate.
Does the ADS6123IRHBR require external decoupling capacitors for its internal reference?
No, the ADS6123IRHBR does not require external decoupling capacitors for its internal reference. As stated in the datasheet features section: "No External Decoupling Required for References." The internal reference is fully integrated and stabilized on-die, eliminating the need for external bypass components typically associated with reference pins.
Can the ADS6123IRHBR operate with a 1.8 V digital supply voltage?
Yes, the ADS6123IRHBR supports a 1.8 V digital supply (DRVDD) when configured for CMOS output mode. The datasheet specifies DRVDD = 1.8 V to 3.3 V for CMOS interface operation, and power consumption data shows 6.1 mA digital supply current at 1.8 V DRVDD (CMOS mode, FS = 80 MSPS).
What output interface options does the ADS6123IRHBR provide?
The ADS6123IRHBR provides two configurable output interfaces: parallel CMOS and double-data-rate LVDS (DDR LVDS). Interface selection is controlled via the SEN pin in parallel mode or register 0x04 in serial mode. Both interfaces support 12-bit data output with programmable drive strength (CMOS) or current (LVDS).
Is the ADS6123IRHBR pin-compatible with other devices in the ADS612X family?
Yes, the ADS6123IRHBR is pin-compatible with ADS6125IRHBR, ADS6124IRHBR, and ADS6122IRHBR. The datasheet explicitly states "Pin Compatible 12-Bit Family (ADS612X)" and confirms identical QFN-32 (RHB) packaging, shared pinout, and function mapping across all variants - enabling drop-in replacement within the same sampling rate tier constraints.
ADS6123IRHBR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Number of Bits:
- 12
- Sampling Rate (Per Second):
- 80M
- Number of Inputs:
- 1
- Input Type:
- Differential
- Data Interface:
- LVDS - Parallel, Parallel
- Configuration:
- S/H-ADC
- Ratio - S/H:ADC:
- 1:1
- Number of A/D Converters:
- 1
- Architecture:
- Pipelined
- Reference Type:
- Internal
- Voltage - Supply, Analog:
- 3V ~ 3.6V
- Voltage - Supply, Digital:
- 1.65V ~ 3.6V
- Features:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Supplier Device Package:
- 32-VQFN (5x5)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
ADS6123IRHBR FAQ
1.How can I place an order for ADS6123IRHBR through Aetrix?
Please submit a Request for Quotation (RFQ) for ADS6123IRHBR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADS6123IRHBR reliable?
The price and inventory of ADS6123IRHBR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADS6123IRHBR is usually 5 days.
3.What payment methods are accepted for ADS6123IRHBR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADS6123IRHBR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADS6123IRHBR?
ADS6123IRHBR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADS6123IRHBR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADS6123IRHBR?
For technical support, including ADS6123IRHBR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADS6123IRHBR requirements.
6.How does Aetrix verify that ADS6123IRHBR is sourced from the original manufacturer or authorized distributors?
All ADS6123IRHBR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADS6123IRHBR meets industry standards.
7.What is the process for return or replacement of ADS6123IRHBR?
All ADS6123IRHBR units undergo pre-shipment inspection (PSI). If there is an issue with ADS6123IRHBR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADS6123IRHBR part is unused and in its original packaging.
Return procedure for ADS6123IRHBR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADS6123IRHBR Tags
-
ADC081C021CIMKX/NOPB
Texas Instruments
-
MCP3021A5T-E/OT
Microchip Technology
-
TLA2024IRUGR
Texas Instruments
-
MCP3221A5T-E/OT
Microchip Technology
-
MCP3221A5T-I/OT
Microchip Technology
-
MCP3221A4T-E/OT
Microchip Technology
-
MCP3221A6T-E/OT
Microchip Technology
-
MCP3221A0T-E/OT
Microchip Technology
-
MCP3221A1T-E/OT
Microchip Technology
-
ADC121S021CIMFX/NOPB
Texas Instruments
-
MCP3001-I/MS
Microchip Technology
-
MCP3001-I/SN
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
