Texas Instruments ADS6123IRHBT

Overview

ADS6123IRHBT from Texas Instruments is a 12-bit, 80 MSPS analog-to-digital converter with DDR LVDS or parallel CMOS outputs, internal reference, and programmable coarse/fine gain. It delivers 71.5 dBFS SINAD at 10 MHz input and 83 dBc SFDR at 170 MHz with 3.5 dB coarse gain, targeting high-performance signal acquisition in wireless infrastructure and radar systems.

For engineers reviewing the ADS6123IRHBT datasheet, ADS6123IRHBT pinout, ADS6123IRHBT application, or ADS6123IRHBT equivalent, this page provides verified specifications, validated package mapping (32-QFN), confirmed timing behavior (9-cycle latency), real-world interface options (LVDS/CMOS), and two documented alternative parts for design flexibility.

Technical Context

The ADS6123IRHBT employs a high-bandwidth sample-and-hold circuit and low-jitter clock buffer to maintain 71.5 dBFS SINAD and 83 dBc SFDR up to 170 MHz input frequency. Its dual-output architecture supports either DDR LVDS (3.3 V DRVDD, 3.5 mA current) or parallel CMOS (1.8–3.3 V DRVDD) with programmable output clock position and drive strength.

Configuration is achieved via 3-wire serial interface (SCLK/SEN/SDATA) or dedicated parallel pins (SCLK/SEN/SDATA/PDN), enabling power-up state definition without firmware. Internal reference eliminates external decoupling; external reference mode supports 1.45–1.55 V VCM with ±20 mV ΔVREF error.

Key Specifications

Pinout & Package

The ADS6123IRHBT is housed in a 32-pin QFN package (RHB designation) with 0.5 mm pitch and exposed thermal pad. Pin functions are defined per TI SLAS560A datasheet Figure 1 and Table 1–3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar high-speed ADC applications.

Compared with ADS6124IRHBT and ADS6122IRHBT, the ADS6123IRHBT offers optimal balance of 80 MSPS throughput, 318 mW power, and 83 dBc SFDR - making it the preferred choice for mid-tier wireless infrastructure and radar designs where performance and efficiency must coexist.

Availability

ADS6123IRHBT is available at Aetrix Electronics and suitable for wireless infrastructure baseband, software-defined radio, and radar system digitization requiring stable component supply across industrial temperature range (–40°C to 85°C).

Supply support for ADS6123IRHBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.

The ADS612X family was designed specifically for high-speed, high-dynamic-range digitization in RF and IF signal chains - emphasizing low jitter, flexible output interfaces, and integrated reference architecture to simplify system-level design.

FAQ

What is the maximum sampling rate supported by the ADS6123IRHBT?

The ADS6123IRHBT supports a maximum sampling rate of 80 MSPS, as specified in the TI SLAS560A datasheet. This rate is guaranteed across the full industrial temperature range (–40°C to 85°C) with AVDD = DRVDD = 3.3 V and proper clock conditioning. Exceeding 80 MSPS may result in degraded AC performance or non-compliance with timing specifications.

Does the ADS6123IRHBT require external decoupling capacitors for its internal reference?

No, the ADS6123IRHBT does not require external decoupling capacitors for its internal reference. As stated in the datasheet features section, the device eliminates traditional reference pins and associated external decoupling. The internal reference (1 V bottom / 2 V top) is fully integrated and stabilized on-die, reducing BOM count and PCB area for the ADS6123IRHBT.

Can the ADS6123IRHBT operate with both LVDS and CMOS digital outputs?

Yes, the ADS6123IRHBT supports both DDR LVDS and parallel CMOS digital outputs. Output interface selection is configurable via the SEN pin (parallel mode) or register 0x00 bit (serial mode). LVDS requires DRVDD = 3.3 V and delivers 225–350 mV differential swing; CMOS supports DRVDD = 1.8–3.3 V with rail-to-rail logic levels - both modes are validated for the ADS6123IRHBT.

What is the latency of the ADS6123IRHBT, and how is it measured?

The ADS6123IRHBT has a fixed latency of 9 clock cycles, measured from the input clock rising edge to valid output data (Figure 1, SLAS560A). This latency is constant across all sampling rates and output modes (LVDS/CMOS), enabling deterministic timing alignment in digital predistortion and radar processing loops. The value is confirmed in the Timing Characteristics table for all ADS612X variants including the ADS6123IRHBT.

How is gain configured on the ADS6123IRHBT, and what impact does it have on performance?

The ADS6123IRHBT supports 3.5 dB coarse gain and up to 6 dB programmable fine gain via register 0x0C or SCLK pin strapping. Coarse gain reduces full-scale input range from 2 VPP to 1.34 VPP, improving SFDR at lower input amplitudes (e.g., 83 dBc at 170 MHz) while slightly reducing SNR. Fine gain allows precise adjustment without altering analog front-end design - a key capability confirmed for the ADS6123IRHBT in the datasheet's Performance Summary table.